Hitachi SH7750 series Hardware Manual page 316

Superh risc engine
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Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The
base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO
by the specified factor.
Bit 5: CKS2
Bit 4: CKS1
0
0
1
1
0
1
Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of
refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified
by the LMTS bit in RTCSR.
Bit 2: OVF
0
1
Note: * If 1 is written, the original value is retained.
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression
of an interrupt request when the OVF flag is set to 1 in RTCSR.
Bit 1: OVIE
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
RFCR has not overflowed the count limit indicated by LMTS
[Clearing condition]
When 0 is written to OVF
RFCR has overflowed the count limit indicated by LMTS
[Setting condition]
When RFCR overflows the count limit set by LMTS*
Description
Interrupt requests initiated by OVF are disabled
Interrupt requests initiated by OVF are enabled
Description
Clock input disabled
Bus clock (CKIO)/4
CKIO/16
CKIO/64
CKIO/256
CKIO/1024
CKIO/2048
CKIO/4096
Rev. 4.0, 04/00, page 305 of 850
(Initial value)
(Initial value)
(Initial value)

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