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1.1
SH7750 Series Features
The SH7750 Series (SH7750, SH7750S) is a 32-bit RISC (reduced instruction set computer)
microprocessor, featuring object code upward-compatibility with SH-1, SH-2, SH-3, and SH-3E
microcomputers. It includes an 8-kbyte instruction cache, a 16-kbyte operand cache with a choice
of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry
fully-associative unified TLB (translation lookaside buffer).
The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM
and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be
reduced by almost 50% compared with 32-bit instructions.
The features of the SH7750 Series are summarized in table 1.1.
Table 1.1
SH7750 Series Features
Item
LSI
Section 1 Overview
Features
•
Operating frequency: 200 MHz, 167 MHz, 133 MHz*
•
Performance
360 MIPS (200 MHz), 300 MIPS (167 MHz), 240 MIPS (133 MHz),
230 MIPS (128 MHz)
1.4 GFLOPS (200 MHz), 1.2 GFLOPS (167 MHz), 0.9 GFLOPS (133
MHz, 128 MHz)
•
Superscalar architecture: Parallel execution of two instructions
•
Voltage
1.95 V (internal), 3.3 V (IO):
HD6417750BP200M, HD6417750SBP200
1.8 V (internal), 3.3 V (IO):
HD6417750F167, HD6417750F167I, HD6417750SF167
1.5 V (internal), 3.3 V (IO):
HD6417750VF128, HD6417750SVF133
•
Packages: 256-pin BGA, 208-pin QFP
•
External buses
Separate 26-bit address and 64-bit data buses
External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus
frequency
Notes: 1. SH7750S only
2. SH7750 only
1
, 128 MHz*
Rev. 4.0, 04/00, page 1 of 850
2
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