Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment
Operation
Access
Size
Address No.
Byte
4n
1
4n+1
1
4n+2
1
4n+3
1
Word
4n
1
4n+2
1
Long-
4n
1
word
Quad-
8n
1
word
8n+4
2
Data Bus
D31–D24
D23–D16
—
—
—
—
Data
7–0
Data
—
7–0
—
—
Data
Data
15–8
7–0
Data
Data
31–24
23–16
Data
Data
31–24
23–16
Data
Data
63–56
55–48
D15–D8
D7–D0
—
Data
7–0
Data
—
7–0
—
—
—
—
Data
Data
15–8
7–0
—
—
Data
Data
15–8
7–0
Data
Data
15–8
7–0
Data
Data
47–40
39–32
Strobe Signals
:(6,
:(6
:(5
:(5,
:(4
:(4,
:(6
:(6
:(5
:(5
:(4
:(4
&$66,
&$66
&$65
&$65,
&$64
&$64,
&$66
&$66
&$65
&$65
&$64
&$64
DQM3
DQM2
DQM1
Asserted
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Rev. 4.0, 04/00, page 317 of 850
:(3,
:(3
:(3
:(3
&$63,
&$63
&$63
&$63
DQM0
Asserted