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19.5
Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 19.7.
Table 19.7 Interrupt Response Time
Item
Time for priority decision and
SR mask bit comparison
Wait time until end of
sequence being executed by
CPU
Time from interrupt exception
handling (save of SR and PC)
until fetch of first instruction of
exception handler is started
Response
Total
time
Minimum
case
Maximum
case
Icyc:
One cycle of internal clock supplied to CPU, etc.
Bcyc: One CKIO cycle
S:
Latency of instruction
Note: Including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is
generated.
Number of States
NMI
RL
1Icyc + 4Bcyc
1Icyc + 7Bcyc
S – 1 (≥ 0) ×
S – 1 (≥ 0) ×
Icyc
Icyc
4 × Icyc
4 × Icyc
5Icyc + 4Bcyc
5Icyc + 7Bcyc
+ (S – 1)Icyc
+ (S – 1)Icyc
13Icyc
19Icyc
36 + S Icyc
60 + S Icyc
Peripheral
Modules
1Icyc + 2Bcyc
S – 1 (≥ 0) ×
Icyc
4 × Icyc
5Icyc + 2Bcyc
+ (S – 1)Icyc
9Icyc
20 + S Icyc
Rev. 4.0, 04/00, page 675 of 850
Notes
When Icyc:
Bcyc = 2:1
When Icyc:
Bcyc = 8:1
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