Hitachi SH7750 series Hardware Manual page 336

SA: Single address DMA
DA: Dual address DMA
CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Figure 13.5 Basic Timing of Basic Interface
T1 T2
Rev. 4.0, 04/00, page 325 of 850