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First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output
cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0
in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2–
TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh
cycle time specification (active/active command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual
reset.
RTCOR value
RTCNT
H'00000000
RTCSR.CKS2–0
Refresh
request
External bus
Rev. 4.0, 04/00, page 368 of 850
≠ 000
= 000
Refresh request cleared
by start of refresh cycle
Figure 13.37 Auto-Refresh Operation
RTCNT cleared to 0 when
RTCNT = RTCOR
Auto-refresh cycle
Time
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