Break Address Register A (Bara) - Hitachi SH7750 Hardware Manual

20.2.2

Break Address Register A (BARA)

Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual
address used in the channel A break conditions. BARA is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address
(bits 31–0) used in the channel A break conditions.
31 30
BAA31 BAA30 BAA29
* *
R/W R/W
23 22
BAA23 BAA22 BAA21
* *
R/W R/W
15 14
BAA15 BAA14 BAA13
* *
R/W R/W
7 6
BAA7 BAA6 BAA5
* *
R/W R/W
29 28 27
BAA28 BAA27
* *
R/W R/W R/W
21 20 19
BAA20 BAA19
* *
R/W R/W R/W
13 12 11
BAA12 BAA11
* *
R/W R/W R/W
5 4
BAA4 BAA3
* *
R/W R/W R/W
26 25
BAA26 BAA25
* * *
R/W R/W
18 17
BAA18 BAA17
* * *
R/W R/W
10 9
BAA10 BAA9
* * *
R/W R/W
3 2 1
BAA2 BAA1
* * *
R/W R/W
Rev. 6.0, 07/02, page 777 of 986
24
BAA24
*
R/W
16
BAA16
*
R/W
8
BAA8
*
R/W
0
BAA0
*
R/W