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CKIO,
internal clock
VDD
RESET
SCK2
MD8, MD7,
MD2–MD0
TRST
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Standby
CKIO,
internal clock
Notes: 1. Oscillation settling time when on-chip resonator is used
2. PLL2 not operating
Figure 23.4 Standby Return Oscillation Settling Time (Return by 5(6(7
Rev. 4.0, 04/00, page 750 of 850
V
min
DD
Figure 23.3 Power-On Oscillation Settling Time
t
RESW
t
OSC1
t
OSCMD
t
OSC2
Stable oscillation
t
SCK2RH
t
MDRH
t
TRSTRH
Stable oscillation
t
RESW
5(6(7)
5(6(7
5(6(7
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