Hitachi SH7750 series Hardware Manual page 352

Superh risc engine

Hide thumbs Also See for SH7750 series:

Table of Contents

(SA: IO ← memory)

Figure 13.19 Burst Access Timing in DRAM EDO Mode

RAS Down Mode: The SH7750 Series has an address comparator for detecting row address

matches in burst mode. By using this address comparator, and also setting RAS down mode

specification bit RASD to 1, it is possible to select RAS down mode, in which 5$6 remains

asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer

than the maximum DRAM 5$6 assert time, the refresh cycle must be decreased to or below the

maximum value of t

RAS down mode can only be used when DRAM is connected in area 3.

In RAS down mode, in the event of an access to an address with a different row address, an access

to a different area, a refresh request, or a bus request, 5$6 is negated and the necessary operation

is performed. When DRAM access is resumed after this, since this is the start of RAS down mode,

the operation starts with row address output. Timing charts are shown in figures 13.20 (1), (2), (3),

Rev. 4.0, 04/00, page 341 of 850

Sh7750sSh7750