Hitachi SH7750 series Hardware Manual page 784

Superh risc engine

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Precharge-sel

(SA: IO → memory)

Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown

by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as

shown by the dotted line.

Figure 23.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst

Rev. 4.0, 04/00, page 776 of 850

Normal write

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