Hitachi SH7750 series Hardware Manual page 364

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Table 13.15 Example of Correspondence between SH7750 Series and Synchronous DRAM

Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0)

SH7750 Series Address Pin

Burst Read: The timing chart for a burst read is shown in figure 13.26. In the following example

it is assumed that four 512K × 16-bit × 2-bank synchronous DRAMs are connected, and a 64-bit

data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output

is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the

rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is

used to wait for completion of auto-precharge based on the READA command inside the

synchronous DRAM; no new access command can be issued to the same bank during this cycle. In

the SH7750 Series, the number of Tpc cycles is determined by the specification of bits TPC2–

TPC0 in MCR, and commands are not issued for the same synchronous DRAM during this

The example in figure 13.26 shows the basic cycle. To connect slower synchronous DRAM, the

cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV

command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits

RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case

of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous

DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA

command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles

Synchronous DRAM Address Pin

BANK select bank address

Address precharge setting

Rev. 4.0, 04/00, page 353 of 850

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