Port Data Register A (Pdtra) - Hitachi SH7750 series Hardware Manual

Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16-
bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin
set to output by bit PBnIO.
Bit 2n + 1: PBnPUP
0
1
Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port is an
input or an output.
Bit 2n: PBnIO
0
1
18.2.2

Port Data Register A (PDTRA)

Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port. When a bit is set as an output, the value written to the PDTRA register is output
from the external pin. When a value is read from the PDTRA register while a bit is set as an input,
the external pin value sampled on the external bus clock is read. When a bit is set as an output, the
value written to the PDTRA register is read.
PDTR is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Description
Bit m (m = 0–15) of 16-bit port is pulled up
Bit m (m = 0–15) of 16-bit port is not pulled up
Description
Bit m (m = 0–15) of 16-bit port is an input
Bit m (m = 0–15) of 16-bit port is an output
15 14
PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT
— —
R/W R/W
7 6
PB7DT PB6DT
— —
R/W R/W
13 12
— —
R/W R/W
5 4
PB5DT PB4DT
— —
R/W R/W
11 10
— —
R/W R/W
3 2
PB3DT PB2DT
— —
R/W R/W
Rev. 4.0, 04/00, page 651 of 850
(Initial value)
(Initial value)
9 8
PB8DT
— —
R/W R/W
1 0
PB1DT PB0DT
— —
R/W R/W