Control Signal Timing - Hitachi SH7750 series Hardware Manual

23.3.2

Control Signal Timing

Table 23.15 Control Signal Timing
Item Symbol Min
%5(4 setup
t
BREQS
time
%5(4 hold
t
BREQH
time
%$&. delay
t
BACKD
time
Bus tri-state t
BOFF1
delay time
Bus tri-state t
BOFF2
delay time
to standby
mode
Bus buffer t
BON1
on time
Bus buffer t
BON2
on time from
standby
STATUS0/1 t
STD1
delay time
STATUS0/1 t
STD2
delay time
to standby
Notes: 1. 64 MHz:
2. 67 MHz:
3. 83 MHz:
4. 100 MHz: V
HD6417750 HD6417750
VF128 SVF133
1
64 MHz* 67 MHz*
Max Min
3.5 — 3.5
1.5 — 1.5
— 10 —
— 15 —
— 2 —
— 15 —
— 1 —
— 11 —
— 2 —
V = 3.0 to 3.6 V, V
DDQ
V = 3.0 to 3.6 V, V
DDQ
V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167, HD6417750SF167)
V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167I)
= 3.0 to 3.6 V, V
DDQ
HD6417750
F167
HD6417750
F167I
HD6417750
SF167
2 3
83 MHz*
Max Min Max
— 3.5 —
— 1.5 —
10 — 8
15 — 12
2 — 2
15 — 12
1 — 1
11 — 9
2 — 2
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –40 to +85°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
HD6417750
BP200M
HD6417750
SBP200
4
100 MHz*
Min Max Unit Figure
3 — ns 23.13
1.5 — ns 23.13
— 6 ns 23.13
— 10 ns 23.13
— 2 t 23.14
cyc
— 10 ns 23.13
— 1 t 23.14
cyc
— 7 ns 23.14
— 2 t 23.14
cyc
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
Rev. 4.0, 04/00, page 755 of 850
Note
BGA