Hitachi SH7750 series Hardware Manual page 768

Note: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
Rev. 4.0, 04/00, page 760 of 850
CKIO
t
A25 – A0
t
t
RD/
t
RSD
D63 – D0
(read)
t
WED1
t
WDD
D63 – D0
(write)
t
t
DACD
DACKn
(SA: IO ← memory)
t
DACKn
(SA: IO → memory)
t
DACKn
(DA)
T1 Tw T2
AD
CSD
RWD
t
RSD
t
RDS
t
WEDF
t
WDD
t
BSD BSD
t t
RDYS
t
DACD
DACDF
t
DACD DACD
t
AD
t
CSD
t
RWD
t
RSD
t
RDH
t
WEDF
t
WDD
RDYH
t
DACD
t
DACDF