Board Id String Registers (0X610 To 0X615); Table 3-6 Watchdog Timer Control Status Register (Wcsr); Table 3-7 Watchdog Timer Control (Wdt) Status Register (Wcsr) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

54 SBC622 Hardware Reference Manual
The mapping of the bits in this register are as follows:

Table 3-6 Watchdog Timer Control Status Register (WCSR)

Field
SERR/RST Select
WDT Timeout Select
WDT Enable
All of these bits default to "0" after system reset. All other bits are Reserved.
The ʺWDT Timeout Selectʺ field is used to select the timeout value of the
Watchdog Timer as follows:

Table 3-7 Watchdog Timer Control (WDT) Status Register (WCSR)

Timeout WCSR [10]
66 s 0
33.6 s 0
2.1 s 0
524 ms 0
262 ms 1
131 ms 1
32.768 ms 1
2.048 ms 1
The ʺSERR/RST Selectʺ bit is used to select whether the WDT generates an SERR#
on the local PCI bus or a system reset. If this bit is set to ʺ0ʺ, the WDT will generate
a system reset. Otherwise, the WDT will make the local PCI bus SERR# signal
active.
The ʺWDT Enableʺ bit is used to enable the Watchdog Timer function. This bit
must be set to ʺ1ʺ in order for the Watchdog Timer to function. Note that since all
registers default to zero after reset, the Watchdog Timer is always disabled after a
reset. The Watchdog Timer must be re‐enabled by the application software after
reset in order for the Watchdog Timer to continue to operate. Once the Watchdog
Timer is enabled, the application software must refresh the Watchdog Timer
within the selected timeout period to prevent a reset or SERR# from being
generated. The Watchdog Timer is refreshed by performing a write to the WDT
Keepalive register (WKPA). The data written is irrelevant.

3.2.13 Board ID String Registers (0x610 to 0x615)

These read back ʺSBC622ʺ.
Bits
WCSR [16]
WCSR [10..8]
WCSR [0]
WCSR [9]
0
0
1
1
0
0
1
1
Read or Write
Read/Write
Read/Write
Read/Write
WCSR [8]
0
1
0
0
1
0
1