Rtc; Compactpci Backplane Interface; Figure 4-2 Smi Processing - GE C2K Hardware Reference Manual

Functional Blocks
FPGA
SMI Mask
Masking
Register
BP_FAL#
MPC7448
BP_DEG#
SMI
Processor
BP_NMI#
CPU_SMI
SMI
WDOG_NMI#
SMI processing
Figure 4-2

4.14 RTC

The C2K includes an M41T62 RTC device to provide and a real-time clock feature for CPU
timekeeping functions. The C2K provides the BATT+ input from the backplane to supply +3.3V
battery backup power to the RTC when the board is powered-down.
NOTE: Power is not maintained to the real-time clock functions when the C2K is removed from
the system.

4.15 CompactPCI Backplane Interface

The C2K employs the PCI 6254 Dual Mode PCI/PCI Bridge to transfer PCI data between the PCI
Bus 1 and the backplane PCI 2.2 compatible cPCI bus. The PCI 6254 provides all the power entry,
system control, and cPCI bus interface wiring defined for 6U system controller and peripheral slot
boards defined in PICMG 2.0. Interface functionality for system controller and peripheral slot
applications is selected in hardware based on slot address information in the backplane.
The PCI 6254 supports either 33MHz and 66MHz bus clocks on the backplane, using 32-bit or
64-bit data transfers and provides bus arbitration logic support for seven peripheral slots. The PCI
6254 also supports 33/66MHz operation on the internal (primary side) PCI bus interface.
NOTE: If the internal PCI bus (primary interface) is operating at 33MHz, the cPCI bus (second-
ary interface) also operates at 33MHz. PCI Bus 1 will operate at 33MHz when it is configured to
+5V VIO or when a 33MHz PMC module is installed on PMC1.
The PCI 6254 is configured to operate in one of two modes: Universal Transparent Mode and
Universal Non-transparent Mode. When the C2K is installed in a system slot, it functions as a
system controller and the PCI 6254 operates in the Universal Transparent Mode. In this mode,
PCI transactions pass transparently from the primary interface to the secondary interface.
4-9 C2K User's Guide
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