Timer 1 Value Register (0X634); Timer 2 Value Register (0X636); Timer 3 Value Register (0X638); Timer 4 Value Register (0X63C) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

58 SBC622 Hardware Reference Manual
The ʺIRQ Enableʺ bit must be set to a ʺ1ʺ for the timer to be able to generate an
interrupt. Each timer has an independently selectable clock source which is
selected by the bit pattern in the ʺTimer x Clock Selectʺ field as follows:

Table 3-14 Timer x Clock Select

Clock Rate
2 MHz
1 MHz
500 KHz
250 KHz
The ʺRead Timerʺ bit selects between reading the current timer value or reading
the timer load value when the timer data is read. Setting this bit to ʺ0ʺ will enable
the reading of the current timer value. Setting this bit to a ʺ1ʺ will enable the
reading of the value that was loaded into the timer.
When the timer generates an interrupt, the ʺInterruptʺ bit is read as a ʺ1ʺ and is
cleared with a write to the appropriate ʺTimer x IRQ Clearʺ register. Alternately,
writing a ʺ0ʺ to TCSR[7] will also clear the interrupt. When this bit is read as a ʺ0ʺ,
the timer has not created an interrupt. When a ʺ1ʺ is written into this bit, a single
interrupt will be generated when the timerʹs ʺIRQ Enableʺ bit is enabled.

3.2.22 Timer 1 Value Register (0x634)

Timer 1 is not implemented on SBC622.

3.2.23 Timer 2 Value Register (0x636)

Timer 2 is not implemented on SBC622.

3.2.24 Timer 3 Value Register (0x638)

Timer 3 is a 32‐bit timer that is located at offset 0x38 from base I/O address 0x600.
When this field is read, the value returned is either the current count value or the
loaded value, depending on the setting of TCSR3[3]. The current timer count
value is latched when either the offset address 0x0C or the offset address 0x08 is
read, depending on the setting of TER[4].

3.2.25 Timer 4 Value Register (0x63C)

Timer 4 is a 32‐bit timer that is located at offset 0x3C from base I/O address 0x600.
When this field is read, the value returned is either the current value or the loaded
value, depending on the setting of TCSR4[3]). The current timer count value is
latched when either the offset address 0x10 or the offset address 0x08 is read,
depending on the setting of TER[4].

3.2.26 Timer 1 IRQ Clear (T1IC)

Timer 1 is not implemented on SBC622.

3.2.27 Timer 2 IRQ Clear (T2IC)

Timer 2 is not implemented on SBC622.
Bit 2
0
0
1
1
Bit 1
0
1
0
1