Mitsubishi Electric MELSEC iQ-R Series Programming Manual page 89

Variable Description
name
CYCLIC TRUE: When the integrated value exceeds the high limit,
the value returns to 0.
FALSE: When the integrated value exceeds the high
limit, the high limit value is held.
*1 The surplus to the integration high limit is added.
For example, the integrated value will be 10 in the following condition: HILMT = 1000, Last integrated value = 990, Current value (IN 
T/T) = 20.
For a REAL data type output value (output variable OUT_R), the number of significant digits is 6 or 7 because
this value is processed in 32-bit single-precision floating-point data. Consequently, a rounding error occurs
when the integrated value exceeds the range of the number of significant digits, and the integral part may not
match with the DINT type output value (output variable OUT_D).
Processing details
■Analog integration processing
When the integration start signal (START) is TRUE and the integration reset signal (RST_) is FALSE, this function block
performs integration processing to the value input from the input variable IN and outputs the result from the output variable.
Integration start signal Integral reset signal
(START) (RST_)
FALSE (Stop) FALSE (Invalid)
TRUE (Valid)
TRUE (Start) FALSE (Invalid)
TRUE (Valid)
T: Execution cycle
ILC: Input low-cut value
A_: Initial value
T: When RANGE is 1, T is 1 (s). When RANGE is 2, T is 60 (s). When RANGE is 3, T is 3600 (s).
Ex.
3
When a value of 0 to 5m /min is input, set RANGE to 2 because the input range is "/min".
The multiplying factor is 1m
• The execution cycle (T) indicates the execution cycle in the property setting of the FBD/LD program for the process
control on the engineering tool, the cycle for starting up the timer in the program execution setting, and the interruption
cycle of the fixed scan interrupt startup.
■Integration start signal
When the integration start signal (START) is FALSE: The integration processing stops.
When the integration start signal (START) is TRUE: The integration processing starts.
■Integration reset signal
When the integration reset signal (RST_) is FALSE: The integrated value is not reset (to the initial value).
When the integration reset signal (RST_) is TRUE: The integrated value is reset and the initial value is output.
■Integration complete signal
Integrated value output (integral part) (OUT_D)  Integration high limit (HILMT): The integration complete signal is TRUE
Integrated value output (integral part) (OUT_D) < Integration high limit (HILMT): The integration complete signal is FALSE.
*1 When CYCLIC is TRUE, TRUE is output for only one cycle.
*1
Input (IN)
Optional
Optional
IN  ILC
IN > ILC
Optional
3
.
Recommended range Initial value
TRUE, FALSE TRUE
Output (OUT_D, OUT_R)
OUT_D, OUT_R = Last value
OUT_D, OUT_R = Initial value (A_)
OUT_D, OUT_R = Last value
OUT_D, OUT_R=(IN×
OUT_D, OUT_R = Initial value (A_)
5.8 Summation (Internal Integer Integration) (M+P_SUM2_)
Set by Data type
User BOOL
ΔT
)+ previous value
T
5 CORRECTION OPERATION
5
*1
.
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