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Philips Semiconductors
Volume 1
19.4.1 RTC interrupts
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all nonmasked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of power-down mode if the RTC is
operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is enabled
for wakeup and its selected event occurs, XTAL1/2 pins associated oscillator wakeup
cycle is started. For details on the RTC based wakeup process see
"Interrupt Wakeup register (INTWAKE - 0xE01F C144)" on page 22
"Wakeup timer" on page
19.4.2 Miscellaneous register group
Table 264
descriptions follow.
Table 264: Miscellaneous registers
Name
ILR
CTC
CCR
CIIR
AMR
CTIME0
CTIME1
CTIME2
19.4.3 Interrupt Location Register (ILR - 0xE002 4000)
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt (see
corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by
the read.
User manual
41.
summarizes the registers located from 0 to 7 of A[6:2]. More detailed
Size Description
2
Interrupt Location. Reading this location
indicates the source of an interrupt. Writing a
one to the appropriate bit at this location clears
the associated interrupt.
15
Clock Tick Counter. Value from the clock
divider.
4
Clock Control Register. Controls the function of
the clock divider.
8
Counter Increment Interrupt. Selects which
counters will generate an interrupt when they
are incremented.
8
Alarm Mask Register. Controls which of the
alarm registers are masked.
32
Consolidated Time Register 0
32
Consolidated Time Register 1
32
Consolidated Time Register 2
Table
Rev. 01 — 15 August 2005
265). Writing a one to the appropriate bit clears the
UM10139
Chapter 19: RTC
Section 3.5.3
and
Section 3.12
Access
Address
R/W
0xE002 4000
RO
0xE002 4004
R/W
0xE002 4008
R/W
0xE002 400C
R/W
0xE002 4010
RO
0xE002 4014
RO
0xE002 4018
RO
0xE002 401C
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
277
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