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Philips LPC2194 User Manual

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LPC2119/2129/2194/2292/2294
USER MANUAL
Preliminary
Supersedes data of 2004 Feb 03
hilips
Semiconductors
INTEGRATED CIRCUITS
2004 May 03

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Summary of Contents for Philips LPC2194

  • Page 1 INTEGRATED CIRCUITS LPC2119/2129/2194/2292/2294 USER MANUAL Preliminary 2004 May 03 Supersedes data of 2004 Feb 03 hilips Semiconductors...
  • Page 2 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 May 03, 2004...

  • Page 3: Table Of Contents

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table of Contents List of Figures ..............7 List of Tables .
  • Page 4 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Vectored Interrupt Controller (VIC) ......... 96 Features .
  • Page 5 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 CAN Controllers and Acceptance Filter ........188 CAN Controllers .
  • Page 6 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Flash Memory System and Programming ........262 Flash Memory System .

  • Page 7: List Of Figures

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 List of Figures Figure 1: LPC2119/2129/2194/2292/2294 Block Diagram ........20 Figure 2: System Memory Map .
  • Page 8 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Figure 55: Exception Handlers............299...

  • Page 9: List Of Tables

    Table 31: Power Control for Peripherals Register for LPC2119/2129/2292 (PCONP - 0xE01FC0C4) ..82 Table 32: Power Control for Peripherals Register for LPC2194/2294 (PCONP - 0xE01FC0C4) ..83 Table 33: VPBDIV Register Map ............86 Table 34: VPB Divider Register (VPBDIV - 0xE01FC100).
  • Page 10 Table 58: Pin Function Select Register 0 for LPC2119/2129/2292 (PINSEL0 - 0xE002C000) ..127 Table 59: Pin Function Select Register 0 for LPC2194/2294 (PINSEL0 - 0xE002C000) ... . . 127 Table 60: Pin Function Select Register 1 for LPC2119/2129/2292 (PINSEL1 - 0xE002C004) .
  • Page 11 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 108: I2C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014) ......175 Table 109: I2C Clock Rate Selections for VPB Clock Divider = 1 .
  • Page 12 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 161: External Match Register (EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C) ....220 Table 162: External Match Control ............220 Table 163: Set and Reset inputs for PWM Flip-Flops .
  • Page 13 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 217: IAP Blank check sector(s) command description ........283 Table 218: IAP Read Part ID command description .

  • Page 14: Document Revision History

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 DOCUMENT REVISION HISTORY 2003 Dec 03: • Prototype LPC2119/2129/2194/2292/2294 User Manual created from the design specification. 2003 Dec 09: • External Memory Controller and Pin Connect Block chapters updated. 2003 Dec 15/16: •...
  • Page 15 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 • IOPIN0 and IOPIN1 tyopografic errors corrected in "System Control Block" chapter • PINSEL2 added to to "Introduction" chapter • T0IR, T0CCR, T0TCR, T1TCR, T0EMR and PCONP updated in "Introduction" chapter • EXTMODE and EXTPOLAR registers added in "Introduction" chapter and updated in "System Control Block" chapter •...

  • Page 16: Introduction

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 1. INTRODUCTION GENERAL DESCRIPTION The LPC2119/2129/2194/2292/2294 are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate.

  • Page 17: Applications

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 APPLICATIONS • Industrial control • Medical systems • Access control • Point-of-sale • Communication gateway • Embedded soft modem • general purpose applications DEVICE INFORMATION Table 1: LPC2119/2129/2194/2292/2294 device information On-chip No. of CAN No.

  • Page 18: Architectural Overview

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURAL OVERVIEW The LPC2119/2129/2194/2292/2294 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral...

  • Page 19: On-Chip Static Ram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ON-CHIP STATIC RAM The LPC2119/2129/2194/2292/2294 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses. The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM.

  • Page 20: Block Diagram

    P3.31:0 Watchdog PWM6:1 PWM0 Timer Real Time System Clock Control * Shared with GPIO When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available LPC2292/2294 only. LPC2194/2294 only. Figure 1: LPC2119/2129/2194/2292/2294 Block Diagram Introduction May 03, 2004...

  • Page 21: Lpc2119/2129/2292/2194/2294 Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 LPC2119/2129/2292/2194/2294 REGISTERS Accesses to registers in LPC2119/2129/2194/2292/2294 is restricted in the following ways: 1) user must NOT attempt to access any register locations not defined. 2) Access to any defined register locations must be strictly for the functions for the registers.

  • Page 22: Table 2: Lpc2119/2129/2194/2292/2294 Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Unused (reserved) bits are marked with "-" and represented as gray fields. Access to them is restricted as already described. Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Watchdog...
  • Page 23 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Int. on Int. on Int. on Int. on 4 reserved (-) bits Cpt.3 Cpt.3 Cpt.3 Cpt.2 T0 Capture falling rising 0xE0004028...
  • Page 24 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Int. on Int. on Int. on Int. on 4 reserved (-) bits Cpt.3 Cpt.3 Cpt.3 Cpt.2 T1 Capture falling rising 0xE0008028...
  • Page 25 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value U0 Line 0xE000C014 U0LSR Status FIFO TEMT THRE 0x60 Register Error U0 Scratch 0xE000C01C U0SCR 8 bit data Pad Register UART1...
  • Page 26 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Int. Int. Int. 0xE0014000 Interrupt Register Int. Int. Int. Int. PWM Timer 0xE0014004 Control Enable Reset Enable Register PWM Timer 0xE0014008...
  • Page 27 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Ena. Ena. Ena. Ena. Ena. Ena. Ena. PWM Latch 0xE0014050 Enable Register Latch Latch Latch Latch Latch Latch Latch I2CONS C Control...
  • Page 28 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value SPI1 Status 0xE0030004 SPIF WCOL ROVR MODF ABRT SPSR Register SPI1 Data 0xE0030008 8 bit data SPDR Register SPI1 Clock 0xE003000C...
  • Page 29 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Day of Month 0xE002402C 5 bit data Register Day of Week 0xE0024030 3 bit data Register Day of Year 0xE0024034 reserved (-) 7 bits...
  • Page 30 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value GPIO 0 Out. 0xE002800C IO0CLR 32 bit data Clear register GPIO PORT1 GPIO 1 Pin 0xE0028010 IO1PIN 32 bit data Value reg.
  • Page 31 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value 24-bit pin configuration data (144 package case) Pin function 0xE002C014 select Reserved bits (64 package case) SEL2 register 2 configuration data...
  • Page 32 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value LUT Error 0xE003C01C LUTerr Error Register CAN Central TCS4:1 Transmit 0x003F 0xE0040000 TxSR Status 3F00 TBS4:1 Register TS4:1 CAN Central DOS4:1...
  • Page 33 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN1 Interrupt 0x0000 0xE0044010 C1IER Enable 0000 TIE3 TIE2 IDIE Register BEIE ALIE EPIE WUIE DOIE TIE1 CAN1 Bus TSEG2 TSEG1...
  • Page 34 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN1 Tx Frame 0x0000 0xE0044030 C1TFI1 Information 0000 Register (buffer 1) PRIO CAN1 Tx 29-bit (FF=1) or Identifier 0x0000 0xE0044034 C1TID1...
  • Page 35 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN1 Tx Frame 0x0000 0xE0044050 C1TFI3 Information 0000 Register (buffer 3) PRIO CAN1 Tx 29-bit (FF=1) or Identifier 0x0000 0xE0044054 C1TID3...
  • Page 36 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN2 Interrupt 0x0000 0xE0048010 C2IER Enable 0000 TIE3 TIE2 IDIE Register BEIE ALIE EPIE WUIE DOIE TIE1 CAN2 Bus TSEG2 TSEG1...
  • Page 37 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN2 Tx Frame 0x0000 0xE0048030 C2TFI1 Information 0000 Register (buffer 1) PRIO CAN2 Tx 29-bit (FF=1) or Identifier 0x0000 0xE0048034 C2TID1...
  • Page 38 (buffer 3) Data 1 Data 8 CAN2 Data 7 Tx Data 0x0000 0xE004805C C2TDB3 Register B Data 6 (buffer 3) Data 5 CAN3 Interface (LPC2194/2294 only) CAN3 Mode 0x0000 0xE004C000 C3MOD Register 0001 CAN3 0xE004C004 C3CMR Command Register STB3 STB2...
  • Page 39 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN3 Interrupt 0x0000 0xE004C010 C3IER Enable 0000 TIE3 TIE2 IDIE Register BEIE ALIE EPIE WUIE DOIE TIE1 CAN3 Bus TSEG2 TSEG1...
  • Page 40 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN3 Tx Frame 0x0000 0xE004C030 C3TFI1 Information 0000 Register (buffer 1) PRIO CAN3 Tx 29-bit (FF=1) or Identifier 0x0000 0xE004C034 C3TID1...
  • Page 41 (buffer 3) Data 1 Data 8 CAN3 Data 7 Tx Data 0x0000 0xE004C05C C3TDB3 Register B Data 6 (buffer 3) Data 5 CAN4 Interface (LPC2194/2294 only) CAN4 Mode 0x0000 0xE0050000 C4MOD Register 0001 CAN4 0xE0050004 C4CMR Command Register STB3 STB2...
  • Page 42 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN4 Interrupt 0x0000 0xE0050010 C4IER Enable 0000 TIE3 TIE2 IDIE Register BEIE ALIE EPIE WUIE DOIE TIE1 CAN4 Bus TSEG2 TSEG1...
  • Page 43 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN4 Tx Frame 0x0000 0xE0050030 C4TFI1 Information 0000 Register (buffer 1) PRIO CAN4 Tx 29-bit (FF=1) or Identifier 0x0000 0xE0050034 C4TID1...
  • Page 44 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value CAN4 Tx Frame 0x0000 0xE0050050 C4TFI3 Information 0000 Register (buffer 3) PRIO CAN4 Tx 29-bit (FF=1) or Identifier 0x0000 0xE0050054 C4TID3...
  • Page 45 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value reserved (-) 19 bits PCAD Power control SPI1 SPI0 0xE01FC0C4 PCONP 0x3BE peripherals PWM0 URT1 URT0 TIM1 TIM0 VPB divider 0xE01FC100...
  • Page 46 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value MW (0x0) Conf. Reg. for 0x0000 0xFFE0000C BCFG3 mem bank 3 FBEF WST2 RBLE WST1 WST1 IDCY Vectored Interrupt Controller - VIC...
  • Page 47 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 2: LPC2119/2129/2194/2292/2294 Registers Address Reset Name Description Access Offset Value Vect. Control 1-bit Vect 0xFFFFF200 5-bit data Cntl0 0 Reg. data Vect. Control 1-bit Vect 0xFFFFF204 5-bit data Cntl1 1 Reg.

  • Page 48: Lpc2119/2129/2292/2294 Memory Addressing

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 2. LPC2119/2129/2292/2294 MEMORY ADDRESSING MEMORY MAPS The LPC2119/2129/2194/2292/2294 incorporates several distinct memory regions, shown in the following figures. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address re-mapping, which is described later in this section.

  • Page 49: Figure 3: Peripheral Memory Map

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 4.0 GB 0xFFFF FFFF AHB Peripherals 0xFFE0 0000 4.0 GB - 2 MB 0xFFDF FFFF Notes: - AHB section is 128 x 16 kB blocks (totaling 2 MB). Reserved - VPB section is 128 x 16 kB blocks (totaling 2 MB).

  • Page 50: Figure 4: Ahb Peripheral Map

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Vectored Interrupt Controller 0xFFFF F000 (4G - 4K) 0xFFFF C000 (AHB peripheral #126) 0xFFFF 8000 (AHB peripheral #125) 0xFFFF 4000 (AHB peripheral #124) 0xFFFF 0000 0xFFE1 0000 (AHB peripheral #3) 0xFFE0 C000...

  • Page 51: Figure 5: Vpb Peripheral Map

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 0xE01F FFFF System Control Block (VPB peripheral #127) 0xE01F C000 (VPB peripherals #14-126) not used 0xE003 8000 10 bit A/D (VPB peripheral #13) 0xE003 4000 SPI1 (VPB peripheral #12) 0xE003 0000 Pin Connect Block...

  • Page 52: Lpc2119/2129/2194/2292/2294 Memory Re-Mapping And Boot Block

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 LPC2119/2129/2194/2292/2294 MEMORY RE-MAPPING AND BOOT BLOCK Memory Map Concepts and Operating Modes The basic concept on the LPC2119/2129/2194/2292/2294 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.
  • Page 53 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Memory Re-Mapping In order to allow for compatibility with future derivatives, the entire Boot Block is mapped to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules will not require changing the location of the Boot Block (which would require changing the Boot Loader code itself) or changing the mapping of the Boot Block interrupt vectors.

  • Page 54: Figure 6: Map Of Lower Memory Is Showing Re-Mapped And Re-Mappable Areas (128 Kb Flash)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 0x8000 0000 2.0 GB 8K byte Boot Block 0x7FFF FFFF (re-mapped from top of Flash memory) 2.0 GB - 8K (Boot Block interrupt vectors) Reserved for On-Chip Memory 0x4000 4000 0x4000 3FFF 16 kB On-Chip SRAM 1.0 GB...

  • Page 55: Prefetch Abort And Data Abort Exceptions

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PREFETCH ABORT AND DATA ABORT EXCEPTIONS The LPC2119/2129/2194/2292/2294 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are: •...

  • Page 56: External Memory Controller (Emc)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 3. EXTERNAL MEMORY CONTROLLER (EMC) This module is available in LPC2292 and LPC2294 only. FEATURES • Supports static memory-mapped devices including RAM, ROM, flash, burst ROM, and some external I/O devices. • Asynchronous page mode read operation in non-clocked memory subsystems •...

  • Page 57: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION Pin Name Type Pin Description Input/ D[31:0] External memory data lines. Output A[23:0] Output External memory address lines. Output Low-active Output Enable signal. BLS[3:0] Output Low-active Byte Lane Select signals.

  • Page 58: Table 8: Bank Configuration Registers 0-3 (Bcfg0-3 - 0Xffe00000-0C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Bank Configuration Registers 0 - 3 (BCFG0-3 - 0xFFE00000-0C) BCFG0-3 Name Function Reset Value This field controls the minimum number of “idle” CCLK cycles that the EMC maintains between read and write accesses in this bank, and between an access in another bank...

  • Page 59: External Memory Interface

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 EXTERNAL MEMORY INTERFACE External memory interface depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register). Furthermore, choice of the memory chip(s) will require an adequate setup of RBLE bit in BCFG register, too. RBLE = 0 in case of 8-bit based external memories, while memory chips capable of accepting 16 or 32 bit wide data will work with RBLE = 1.

  • Page 60: Figure 8: 16 Bit Bank External Memory Interfaces

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BLS[1] BLS[0] BLS[1] BLS[0] D[15:0] IO[15:0] D[15:8] IO[7:0] D[7:0] IO[7:0] A[a_m:0] A[a_m:0] A[a_m:0] A[a_b:1] A[a_b:1] a) 16 bit wide memory bank interfaced a) 16 bit wide memory bank interfaced to 8 bit memory chips...

  • Page 61: Typical Bus Sequences

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 TYPICAL BUS SEQUENCES Following figures show typical external read and write access cycles. XCLK is the clock signal avalable on P3.23. While not necessary used by external memory, In these examples it is used to provide the time reference (XCLK and CCLK were set to have the same frequency).

  • Page 62: External Memory Selection

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 EXTERNAL MEMORY SELECTION Based on the description of the EMC operation and external memory in general (appropriate read and write access times t respecitely), the following table can be constructed and used for external memory selection. t...
  • Page 63 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 External Memory Controller (EMC) May 03, 2004...

  • Page 64: System Control Block

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 4. SYSTEM CONTROL BLOCK SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: •...
  • Page 65 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 System Control Block May 03, 2004...

  • Page 66: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 12: Summary of System Control Registers Reset Name...

  • Page 67: Crystal Oscillator

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 CRYSTAL OSCILLATOR While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by LPC2119/2129/2194/ 2292/2294 if supplied to its input XTAL1 pin, this microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only.

  • Page 68: Figure 13: Fosc Selection Algorithm

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 13: Recommended values for C in oscillation mode (crystal and external components parameters) X1/X2 Fundamental Oscillation Crystal Load Max. Crystal Series External Load Frequency F Capacitance C Resistence R Capacitors C <...

  • Page 69: External Interrupt Inputs

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 EXTERNAL INTERRUPT INPUTS The LPC2119/2129/2194/2292/2294 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from the Power Down mode.

  • Page 70: Table 15: External Interrupt Flag Register (Extint - 0Xe01Fc140)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 15: External Interrupt Flag Register (EXTINT - 0xE01FC140) Reset EXTINT Function Description Value In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.

  • Page 71: Table 16: External Interrupt Wakeup Register (Extwake - 0Xe01Fc144)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) Reset EXTWAKE Function Description Value EXTWAKE0 When one, assertion of EINT0 will wake up the processor from Power Down mode. EXTWAKE1 When one, assertion of EINT1 will wake up the processor from Power Down mode.

  • Page 72: Table 18: External Interrupt Polarity Register (Extpolar - 0Xe01Fc14C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 18: External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C) Reset EXTPOLAR Function Description Value When 0, EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). EXTPOLAR0 When 1, EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).

  • Page 73: Figure 14: External Interrupt Logic

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Wakeup Enable VPB Read (one bit of EXTWAKE) of EXTWAKE EINTi to VPB Bus Data Wakeup Timer (Figure 16) Glitch EINTi Filter pclk Interrupt Flag (one bit of EXTINT) EXTPOLARi to VIC...

  • Page 74: Memory Mapping Control

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 MEMORY MAPPING CONTROL The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. This allows code running in different memory spaces to have control of the interrupts.

  • Page 75: Pll (Phase Locked Loop)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PLL (PHASE LOCKED LOOP) The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up into the cclk with the range of 10 MHz to 60 MHz using a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2119/2129/2194/2292/2294 due to the upper frequency limit of the CPU).

  • Page 76: Figure 15: Pll Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Clock PLLC Synchronization PLLE Direct PSEL[1:0] Bypass Phase- PLOCK Frequency Detector cclk fout Div-by-M msel<4:0> MSEL[4:0] Figure 15: PLL Block Diagram PLL Control Register (PLLCON - 0xE01FC080) The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values.

  • Page 77: Table 22: Pll Control Register (Pllcon - 0Xe01Fc080)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 22: PLL Control Register (PLLCON - 0xE01FC080) Reset PLLCON Function Description Value PLL Enable. When one, and after a valid PLL feed, this bit will activate the PLL and PLLE allow it to lock to the requested frequency. See PLLSTAT register, Table 24.

  • Page 78: Table 24: Pll Status Register (Pllstat - 0Xe01Fc088)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 24: PLL Status Register (PLLSTAT - 0xE01FC088) Reset PLLSTAT Function Description Value MSEL4:0 Read-back for the PLL Multiplier value. This is the value currently used by the PLL. PSEL1:0 Read-back for the PLL Divider value. This is the value currently used by the PLL.

  • Page 79: Table 26: Pll Feed Register (Pllfeed - 0Xe01Fc08C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 The two writes must be in the correct sequence, and must be consecutive VPB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not become effective.

  • Page 80: Table 27: Pll Divider Values

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Procedure for Determining PLL Settings If a particular application uses the PLL, its configuration may be determined as follows: 1. Choose the desired processor operating frequency (cclk). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc.

  • Page 81: Power Control

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 POWER CONTROL The LPC2119/2129/2194/2292/2294 supports two reduced power modes: Idle mode and Power Down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution.

  • Page 82: Table 30: Power Control Register (Pcon - 0Xe01Fc0C0)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 30: Power Control Register (PCON - 0xE01FC0C0) Reset PCON Function Description Value Idle mode - when 1, this bit causes the processor clock to be stopped, while on-chip peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution.

  • Page 83: Table 32: Power Control For Peripherals Register For Lpc2194/2294 (Pconp - 0Xe01Fc0C4)

    PCCAN2 When 1, CAN Controller 2 is enabled. When 0, it is disabled to save power. Reserved, user software should not write ones to reserved bits. The value read from a reserved 31:15 Reserved bit is not defined. Table 32: Power Control for Peripherals Register for LPC2194/2294 (PCONP - 0xE01FC0C4) Reset PCONP Function Description Value Reserved, user software should not write ones to reserved bits.

  • Page 84: Power Control Usage Notes

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 POWER CONTROL USAGE NOTES After every reset, PCONP register contains the value that enables all interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, user’s application has no need to access the PCONP in order to start using any of the on-board peripherals.

  • Page 85: Reset

    Oscillator EINT1 Wakeup EINT2 Wakeup in PCON Output (F EINT3 Wakeup Write "1" from VPB CAN1 Wakeup CAN2 Wakeup CAN3 Wakeup* Reset CAN4 Wakeup* *LPC2194/2292/2294 only Figure 16: Reset Block Diagram including Wakeup Timer System Control Block May 03, 2004...

  • Page 86: Vpb Divider

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 VPB DIVIDER The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). The VPB Divider serves two purposes. The first is to provides peripherals with desired pclk via VPB bus so that they can operate at the speed chosen for the ARM processor.

  • Page 87: Figure 17: Vpb Divider Connections

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Crystal Oscillator Processor Clock External Clock Source (cclk) VPB Divider VPB Clock (pclk) Figure 17: VPB Divider Connections System Control Block May 03, 2004...

  • Page 88: Wakeup Timer

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 WAKEUP TIMER The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason.
  • Page 89 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 System Control Block May 03, 2004...

  • Page 90: Memory Accelerator Module (Mam)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 5. MEMORY ACCELERATOR MODULE (MAM) INTRODUCTION Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls. The method used is to split the Flash memory into two banks, each capable of independent accesses.

  • Page 91: Figure 18: Simplified Block Diagram Of The Memory Accelerator Module

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Flash programming operations are not controlled by the Memory Accelerator Module, but are handled as a separate function. A “boot block” sector contains Flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow serial programming of the Flash memory.

  • Page 92: Memory Accelerator Module Operating Modes

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 In order to preclude the possibility of stale data being read from the Flash memory, the MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation. Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed.

  • Page 93: Mam Configuration

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 MAM CONFIGURATION After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.

  • Page 94: Mam Usage Notes

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 MAM Control Register (MAMCR - 0xE01FC000) Two configuration bits select the three MAM operating modes, as shown in Table 38. Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required.
  • Page 95 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Memory Accelerator Module (MAM) May 03, 2004...

  • Page 96: Vectored Interrupt Controller (Vic)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 6. VECTORED INTERRUPT CONTROLLER (VIC) FEATURES • ARM PrimeCell™ Vectored Interrupt Controller • 32 interrupt request inputs • 16 vectored IRQ interrupts • 16 priority levels dynamically assigned to interrupt requests • Software interrupt generation...

  • Page 97: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The VIC implements the registers shown in Table 40. More detailed descriptions follow. Table 40: VIC Register Map Reset Name Description Access Address Value* IRQ Status Register. This register reads out the state of those interrupt...
  • Page 98 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 40: VIC Register Map Reset Name Description Access Address Value* VICVectAddr10 Vector address 10 register 0xFFFF F128 VICVectAddr11 Vector address 11 register 0xFFFF F12C VICVectAddr12 Vector address 12 register 0xFFFF F130...

  • Page 99: Vic Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 VIC REGISTERS This section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to those most abstracted for use by software. For most people, this is also the best order to read about the registers when learning the VIC.

  • Page 100: Table 44: Interrupt Enable Register (Vicintenable - 0Xfffff010, Read/Write)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Interrupt Enable Register (VICIntEnable - 0xFFFFF010, Read/Write) This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ. Table 44: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write)

  • Page 101: Table 48: Irq Status Register (Vicfiqstatus - 0Xfffff004, Read-Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only) This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

  • Page 102: Table 52: Vector Address Register (Vicvectaddr - 0Xfffff030, Read/Write)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write) When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read. Table 52: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)

  • Page 103: Interrupt Sources

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 INTERRUPT SOURCES Table 54 lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
  • Page 104 Block Flag(s) VIC Channel # CAN and Acceptance Filter (1 ORed CAN, LUTerr int) CAN1 Tx CAN2 Tx CAN3 Tx (LPC2194/2292/2294 only, otherwise Reserved) CAN4 Tx (LPC2194/2292/2294 only, otherwise Reserved) Reserved 24-25 CAN1 Rx CAN2 Rx CAN3 Rx (LPC2194/2292/2294 only, otherwise Reserved)

  • Page 105: Figure 19: Block Diagram Of The Vectored Interrupt Controller

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 nVICFIQIN Interrupt Request, Masking, and Selection Non-vectored FIQ Interrupt Logic SoftIntClear IntEnableClear [31:0] [31:0] nVICFIQ FIQStatus [31:0] SoftInt IntEnable FIQStatus [31:0] [31:0] [31:0] VICINT IRQStatus SOURCE Non-vectored IRQ Interrupt Logic [31:0] [31:0]...

  • Page 106: Spurious Interrupts

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 SPURIOUS INTERRUPTS Spurious interrupts are possible to occur in the ARM7TDMI based microcontroller such as the LPC2119/2129/2194/2292/2294 due to the asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC.
  • Page 107 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 This means that, on entry to the IRQ interrupt service routine, one can see the unusual effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the example above, the F bit will also be set in both the CPSR and SPSR. This means that FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly re-enabled.
  • Page 108 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Solution 2: Disable IRQs and FIQs using separate writes to the CPSR, eg: r0, cpsr r0, r0, #I_Bit ;disable IRQs cpsr_c, r0 r0, r0, #F_Bit ;disable FIQs cpsr_c, r0 This is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all).

  • Page 109: Vic Usage Notes

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 VIC USAGE NOTES If user’s code is runing from the on-chip RAM and an aplication uses interrupts, interrupt vectors must be re-mapped to flash address 0x0. This is necessary because all the exception vectors are located at addresses 0x0 and above. This is easily achieved by configuring MEMMAP register (located in System Control Block) to User RAM mode.

  • Page 110: Pin Configuration

    P1.20/TRACESYNC P0.21/PWM5/RD3*/CAP1.3 P0.17/CAP1.2 /SCK1/MAT1.2 P0.22/TD3*/CAP0.0/MAT0.0 P0.16/EINT0/MAT0.2/CAP0.2 P0.23/RD2 P0.15/RI1/EINT2 P1.19/TRACEPKT3 P1.21/PIPESTAT0 P0.24/TD2 P0.14/DCD1/EINT1 P1.18/TRACEPKT2 P1.22/PIPESTAT1 P0.25/RD1 P0.13/DTR1/MAT1.1/TD4* P0.12/DSR1/MAT1.0/RD4* P0.27/AIN0/CAP0.1/MAT0.1 P0.11/CTS1/CAP1.1 P1.17/TRACEPKT1 P1.23/PIPESTAT2 P0.28/AIN1/CAP0.2/MAT0.2 P0.10/RTS1/CAP1.0 P0.29/AIN2/CAP0.3/MAT0.3 P0.9/RxD1/PWM6/EINT3 P0.30/AIN3/EINT3/CAP0.0 P0.8/TxD1/PWM4 P1.16/TRACEPKT0 *LPC2194 only Figure 20: LPC2119/2129/2194 64-pin package Pin Configuration May 03, 2004...

  • Page 111: Pin Description For Lpc2119/2129/2194

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION FOR LPC2119/2129/2194 Pin description for LPC2119/2129/2194 and a brief of corresponding functions are shown in the following table. Table 55: Pin description for LPC2119/2129/2194 LQFP64 Type Description Name Pin # Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit.
  • Page 112 Capture input for TIMER1, channel 1. P0.12 DSR1 Data Set Ready input for UART1. MAT1.0 Match output for TIMER1, channel 0. CAN4 receiver input (available in LPC2194 only). P0.13 DTR1 Data Terminal Ready output for UART1. MAT1.1 Match output for TIMER1, channel 1.
  • Page 113 LPC2119/2129/2194/2292/2294 Table 55: Pin description for LPC2119/2129/2194 LQFP64 Type Description Name Pin # P0.22 CAN3 transmitter output (available in LPC2194 only) CAP0.0 Capture input for TIMER0, channel 0. MAT0.0 Match output for TIMER0, channel 0. P0.23 CAN2 receiver input. P0.24 CAN2 transmitter output.
  • Page 114 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 55: Pin description for LPC2119/2129/2194 LQFP64 Type Description Name Pin # P1.21 PIPESTAT0 Pipeline Status, bit 0. Standard I/O port with internal pull-up. P1.22 PIPESTAT1 Pipeline Status, bit 1. Standard I/O port with internal pull-up.
  • Page 115 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 55: Pin description for LPC2119/2129/2194 LQFP64 Type Description Name Pin # 17, 49 1.8V Core Power Supply: This is the power supply voltage for internal circuitry. Analog 1.8V Core Power Supply: This is the power supply voltage for internal circuitry. This should be nominally the same voltage as V18 but should be isolated to minimize noise and error.

  • Page 116: Lpc2292/2294 Pinout

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 LPC2292/2294 PINOUT P2.3/D3 P2.22/D22 P2.2/D2 P2.1/D1 P0.21/PWM5/RD3 /CAP1.3 P0.22/TD3 /CAP0.0/MAT0.0 P0.23/RD2 P1.20/TRACESYNC P1.19/TRACEPKT3 P0.17/CAP1.2/SCK1/MAT1.2 P0.24/TD2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2 P2.23/D23 P2.0/D0 P2.24/D24 P3.30/BLS1 P2.25/D25 P3.31/BLS0 P2.26/D26/BOOT0 P1.21/PIPESTAT0 P1.18/TRACEPKT2 P2.27/D27/BOOT1 P0.14/DCD1/EINT1 P2.28/D28 P1.0/CS0 P2.29/D29 P1.1/OE P2.30/D30/AIN4...

  • Page 117: Pin Description For Lpc2292/2294

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION FOR LPC2292/2294 Pin description for LPC2292/2294 and a brief of corresponding functions are shown in the following table.Pin Description Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit.
  • Page 118 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P0.10 RTS1 Request to Send output for UART1. CAP1.0 Capture input for TIMER1, channel 0. P0.11 CTS1 Clear to Send input for UART1.
  • Page 119 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P0.22 CAN3 transmitter output (available in LPC2294 only). CAP0.0 Capture input for TIMER0, channel 0. MAT0.0 Match output for TIMER0, channel 0.
  • Page 120 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P1.19 TRACEPKT3Trace Packet, bit 3. Standard I/O port with internal pull-up. P1.20 TRACESYNCTrace Synchronization. Standard I/O port with internal pull-up.
  • Page 121 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P2.0 External memory data line 0. P2.1 External memory data line 1. P2.2 External memory data line 2. P2.3 External memory data line 3.
  • Page 122 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P2.22 External memory data line 22. P2.23 External memory data line 23. P2.24 External memory data line 24. P2.25 External memory data line 25.
  • Page 123 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P3.1 External memory address line 1. P3.2 External memory address line 2. P3.3 External memory address line 3. P3.4 External memory address line 4.
  • Page 124 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P3.23 External memory address line 23. XCLK Clock output. P3.24 Low-active Chip Select 3 signal. (Bank 3 addresses range 8300 0000 - 83FF FFFF) P3.25...
  • Page 125 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # 37, 110 1.8V Core Power Supply: This is the power supply voltage for internal circuitry. Analog 1.8V Core Power Supply: This is the power supply voltage for internal circuitry.

  • Page 126: Pin Connect Block

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 8. PIN CONNECT BLOCK FEATURES • Allows individual pin configuration APPLICATIONS The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions. DESCRIPTION The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

  • Page 127: Table 58: Pin Function Select Register 0 For Lpc2119/2129/2292 (Pinsel0 - 0Xe002C000)

    CD (UART1) EINT1 Reserved 31:30 P0.15 GPIO Port 0.15 RI (UART1) EINT2 Reserved Table 59: Pin Function Select Register 0 for LPC2194/2294 (PINSEL0 - 0xE002C000) Reset PINSEL0 Function when 00 Function when 01 Function when 10 Function when 11 Name Value P0.0...

  • Page 128: Table 60: Pin Function Select Register 1 For Lpc2119/2129/2292 (Pinsel1 - 0Xe002C004)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 59: Pin Function Select Register 0 for LPC2194/2294 (PINSEL0 - 0xE002C000) Reset PINSEL0 Function when 00 Function when 01 Function when 10 Function when 11 Name Value 21:20 P0.10 GPIO Port 0.10 RTS (UART1) Capture 1.0 (TIMER1)

  • Page 129: Table 61: Pin Function Select Register 1 For Lpc2194/2294 (Pinsel1 - 0Xe002C004)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 62: Pin Function Select Register 1 for LPC2194/2294 (PINSEL1 - 0xE002C004) Reset PINSEL1 Function when 00 Function when 01 Function when 10 Function when 11 Name Value P0.16 GPIO Port 0.16 EINT0 Match 0.2 (TIMER0)
  • Page 130 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 63: Pin Function Select Register 2 for LPC2119/2129/2194 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value Reserved. Note: These bits must not be altered at any time. Changing them may result in an incorrect code execution.

  • Page 131: Table 63: Pin Function Select Register 2 For Lpc2292/2294 (Pinsel2 - 0Xe002C014)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 64: Pin Function Select Register 2 for LPC2292/2294 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value Reserved. When 0, pins P1.36:26 are used as GPIO pins. When 1, P1.31:26 are used as a Debug port.

  • Page 132: Table 64: Pin Function Select Register Bits

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 64: Pin Function Select Register 2 for LPC2292/2294 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value Controls the number of pins among P3.23/A23/XCLK and P3.22:2/A2.22:2 that are address lines: 000 = None 100 = A11:2 are address lines.

  • Page 133: Boot Control On 144-Pin Package

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BOOT CONTROL ON 144-PIN PACKAGE In the 144-pin package only, the state of the BOOT1:0 pins, while RESET is low, controls booting and initial operation. Internal pullups in the receivers ensure high state if a pin is left unconnected. Board designers can connect weak pulldown resistors...

  • Page 134: Gpio

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 9. GPIO FEATURES • Direction control of individual bits • Separate control of output set and clear • All I/O default to inputs after reset APPLICATIONS • General purpose I/O • Driving LEDs, or other indicators •...

  • Page 135: Table 67: Gpio Register Map

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 68: GPIO Register Map PORT0 PORT1 PORT2 PORT3 Generic Reset Description Access Address & Address & Address & Address & Name Value Name Name Name Name GPIO Port Pin value register. The...

  • Page 136: Table 68: Gpio Pin Value Register (Io0Pin - 0Xe0028000, Io1Pin - 0Xe0028010, Io2Pin - 0Xe0028020, Io3Pin - 0Xe0028030)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010, IO2PIN - 0xE0028020, IO3PIN - 0xE0028030) This register provides the value of the GPIO pins. Register’s value reflects any outside world influence on the GPIO configured pins only.

  • Page 137: Gpio Usage Notes

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 (IO0CLR - 0xE002800C, IO1CLR - 0xE002801C, IO2CLR - 0xE002802C, IO3CLR - 0xE002803C) This register is used to produce a LOW level at port pins if they are configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register.
  • Page 138 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Solution utilizing access to IO0SET and IO0CLR will take more steps compared to a single IO0PIN write access. GPIO May 03, 2004...
  • Page 139 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 GPIO May 03, 2004...

  • Page 140: 10. Uart0

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 10. UART0 FEATURES • 16 byte Receive and Transmit FIFOs. • Register locations conform to ‘550 industry standard. • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. • Built-in baud rate generator.

  • Page 141: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION Table 74: UART0 Register Map Reset Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access Address Value* Receiver 0xE000C000 U0RBR...

  • Page 142: Table 74: Uart0 Receiver Buffer Register (U0Rbr - 0Xe000C000 When Dlab = 0, Read Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 75: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only) Reset U0RBR Function Description Value Receiver Buffer The UART0 Receiver Buffer Register contains the oldest received byte in the UART0 Rx...

  • Page 143: Table 78: Uart0 Interrupt Enable Register Bit Descriptions (U0Ier - 0Xe000C004 When Dlab = 0)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART0 Interrupt Enable Register (U0IER - 0xE000C004 when DLAB = 0) The U0IER is used to enable the four UART0 interrupt sources. Table 79: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0)

  • Page 144: Table 80: Uart0 Interrupt Handling

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 The UART0 RLS interrupt (U0IIR3:1=011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART0 Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART0 Rx error condition that set the interrupt can be observed via U0LSR4:1.

  • Page 145: Table 81: Uart0 Fifo Control Register Bit Descriptions (U0Fcr - 0Xe000C008)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART0 FIFO Control Register (U0FCR - 0xE000C008) The U0FCR controls the operation of the UART0 Rx and Tx FIFOs. Table 82: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) Reset U0FCR...

  • Page 146: Table 82: Uart0 Line Control Register Bit Descriptions (U0Lcr - 0Xe000C00C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART0 Line Control Register (U0LCR - 0xE000C00C) The U0LCR determines the format of the data character that is to be transmitted or received. Table 83: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C)

  • Page 147: Table 83: Uart0 Line Status Register Bit Descriptions (U0Lsr - 0Xe000C014, Read Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 84: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) Reset U0LSR Function Description Value 0: U0RBR is empty Receiver 1: U0RBR contains valid data Data Ready U0LSR0 is set when the U0RBR holds an unread character and is cleared when the (RDR) UART0 RBR FIFO is empty.

  • Page 148: Table 84: Uart0 Scratchpad Register (U0Scr - 0Xe000C01C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART0 Scratch Pad Register (U0SCR - 0xE000C01C) The U0SCR has no effect on the UART0 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

  • Page 149: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE The architecture of the UART0 is shown below in the block diagram. The VPB interface provides a communications link between the CPU or host and the UART0. The UART0 receiver block, U0Rx, monitors the serial input line, RxD0, for valid input. The UART0 Rx Shift Register (U0RSR) accepts valid characters via RxD0.

  • Page 150: Figure 22: Uart0 Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 U0Tx NTXRDY TxD0 U0THR U0TSR U0BRG U0DLL NBAUDOUT U0DLM RCLK U0Rx NRXRDY INTERRUPT RxD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0] Interface pclk Figure 22: UART0 Block Diagram...
  • Page 151 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART0 May 03, 2004...

  • Page 152: 11. Uart1

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 11. UART1 FEATURES • UART1 is identical to UART0, with the addition of a modem interface. • 16 byte Receive and Transmit FIFOs. • Register locations conform to ‘550 industry standard. • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

  • Page 153: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION Table 87: UART1 Register Map Reset Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access Address Value* Receiver 0xE0010000 U1RBR...

  • Page 154: Table 87: Uart1 Receiver Buffer Register (U1Rbr - 0Xe0010000 When Dlab = 0, Read Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only) The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.

  • Page 155: Table 90: Uart1 Divisor Latch Msb Register (U1Dlm - 0Xe0010004 When Dlab = 1)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 91: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1) Reset U1DLM Function Description Value Divisor Latch The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the MSB Register baud rate of the UART1.

  • Page 156: Table 92: Uart1 Interrupt Identification Register Bit Descriptions (Iir - 0Xe0010008, Read Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Interrupt Identification Register (U1IIR - 0xE0010008, Read Only) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access.

  • Page 157: Table 93: Uart1 Interrupt Handling

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 94: UART1 Interrupt Handling Interrupt Interrupt Interrupt U1IIR[3:0] Priority Type Source Reset 0001 none none Rx Line Status / 0110 Highest OE or PE or FE or BI U1LSR Read Error...

  • Page 158: Table 94: Uart1 Fcr Bit Descriptions (U1Fcr - 0Xe0010008)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 FIFO Control Register (U1FCR - 0xE0010008) The U1FCR controls the operation of the UART1 Rx and Tx FIFOs. Table 95: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) Reset U1FCR Function Description Value Active high enable for both UART1 Rx and Tx FIFOs and U1FCR7:1 access.

  • Page 159: Table 95: Uart1 Line Control Register Bit Descriptions (U1Lcr - 0Xe001000C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Line Control Register (U1LCR - 0xE001000C) The U1LCR determines the format of the data character that is to be transmitted or received. Table 96: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C)

  • Page 160: Table 96: Uart1 Modem Control Register Bit Descriptions (U1Mcr - 0Xe0010010)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Modem Control Register (U1MCR - 0xE0010010) The U1MCR enables the modem loopback mode and controls the modem output signals. Table 97: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) Reset...

  • Page 161: Table 97: Uart1 Line Status Register Bit Descriptions (U1Lsr - 0Xe0010014, Read Only)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Line Status Register (U1LSR - 0xE0010014, Read Only) The U1LSR is a read-only register that provides status information on the UART1 Tx and Rx blocks. Table 98: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only)

  • Page 162: Table 98: Uart1 Modem Status Register Bit Descriptions (U1Msr - 0X0Xe0010018)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Modem Status Register (U1MSR - 0x0xE0010018) The U1MSR is a read-only register that provides status information on the modem input signals. U1MSR3:0 is cleared on U1MSR read. Note that modem signals have no direct affect on UART1 operation, they facilitate software implementation of modem signal operations.

  • Page 163: Table 99: Uart1 Scratchpad Register (U1Scr - 0Xe001001C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 UART1 Scratch Pad Register (U1SCR - 0xE001001C) The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred.

  • Page 164: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE The architecture of the UART1 is shown below in the block diagram. The VPB interface provides a communications link between the CPU or host and the UART1. The UART1 receiver block, U1Rx, monitors the serial input line, RxD1, for valid input. The UART1 Rx Shift Register (U1RSR) accepts valid characters via RxD1.

  • Page 165: Figure 23: Uart1 Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 MODEM U1Tx NTXRDY TxD1 U1THR U1TSR U1MSR U1BRG U1DLL NBAUDOUT U1MCR U1DLM RCLK U1Rx NRXRDY INTERRUPT RxD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0]...

  • Page 166: I2C Interface

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 12. I C INTERFACE FEATURES • Standard I C compliant bus interface. • Easy to configure as Master, Slave, or Master/Slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves.

  • Page 167: Figure 24: I2C Bus Configuration

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 C Bus Other Device with I Other Device with I LPC2119/2129/2194 Interface Interface LPC2292/2294 Figure 24: I C Bus Configuration C Operating Modes Master Transmitter Mode: In this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, I2CONSET must be initialized as shown in Figure 25.

  • Page 168: Figure 26: Format In The Master Transmitter Mode

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 18h, 20h, or 38h for the master mode, or 68h, 78h, or 0B0h if the slave mode was enabled (by setting AA=1).

  • Page 169: Figure 28: A Master Receiver Switch To Master Transmitter After Sending Repeated Start

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 DATA DATA DATA Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) A = Not Acknowledge (SDA high) S = START condition P = STOP Condition From Master to Slave...

  • Page 170: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 DATA Slave Address DATA P/RS Data Transferred "0" - Write (n Bytes + Acknowledge) "1" - Read A = Acknowledge (SDA low) A = Not Acknowledge (SDA high) From Master to Slave...

  • Page 171: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The I C interface contains 7 registers as shown in Table 102. below. Table 102: I C Register Map Name Description Access Reset Value* Address I2CONSET C Control Set Register...
  • Page 172 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 C Control Set Register (I2CONSET - 0xE001C000) AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 1.

  • Page 173: Table 102: I2C Control Set Register (I2Conset - 0Xe001C000)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 I2EN I C Interface Enable. When I2EN is 1, the I C function is enabled. I2EN can be cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I C function is disabled.

  • Page 174: Table 104: I2C Status Register (I2Stat - 0Xe001C004)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 C Status Register (I2STAT - 0xE001C004) This is a read-only register. It contains the status code of the I C interface. The least three bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and the SI bit is not set. All other 25 status codes correspond to defined I C states.

  • Page 175: Table 107: I2C Scl High Duty Cycle Register (I2Sclh - 0Xe001C010)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 C SCL Duty Cycle Registers (I2SCLH - 0xE001C010 and I2SCLL - 0xE001C014) Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate. I2SCLH defines the number of pclk cycles for SCL high, I2SCLL defines the number of pclk cycles for SCL low.

  • Page 176: Table 110: I2C Clock Rate Selections For Vpb Clock Divider = 2

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 111: I2C Clock Rate Selections for VPB Clock Divider = 2 Bit Frequency (kHz) At f (MHz) & VPB Clock Divider = 2 I2SCLL+ CCLK I2SCLH 320.0 400.0 160.0 200.0 400.0 106.667...

  • Page 177: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE I2ADR Address Register Comparator Input Filter Shift Register Output Stage I2DAT Bit Counter / Arbitration & pclk Sync Logic Input Filter Timing & Control Logic Interrupt Output Serial Clock Stage Generator I2CONSET Control Register &...

  • Page 178: Spi Interface

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 13. SPI INTERFACE FEATURES • Two complete and independent SPI cintrollers • Compliant with Serial Peripheral Interface (SPI) specification. • Synchronous, Serial, Full Duplex Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate.

  • Page 179: Figure 33: Spi Data Transfer Format (Cpha = 0 And Cpha = 1)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 MOSI (CPHA = 0) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...
  • Page 180 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 When a device is a master, the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted. At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
  • Page 181 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave. This process assumes that any prior data transfer has already completed. It is required that the system clock driving the SPI logic be at least 8X faster than the SPI.

  • Page 182: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION Table 114: SPI Pin Description Pin Name Type Pin Description Serial Clock. The SPI is a clock signal used to synchronize the transfer of data across the SPI Input/ interface. The SPI is always driven by the master and received by the slave. The clock is...

  • Page 183: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The SPI contains 5 registers as shown in Table 115. All registers are byte, half word and word accessible. Table 115: SPI Register Map SPI0 SPI1 Generic Reset Description Access Address &...

  • Page 184: Table 116: Spi Status Register (S0Spsr - 0Xe0020004, S1Spsr - 0Xe0030004)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004) The SPSR register controls the operation of the SPI as per the configuration bits setting. Table 117: SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004)

  • Page 185: Table 119: Spi Interrupt Register (S0Spint - 0Xe002001C, S1Spint - 0Xe003001C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 The SPI rate may be calculated as: PCLK rate / SPCCR value. The pclk rate is CCLK / VPB divider rate as determined by the VPBDIV register contents. SPI Interrupt Register (S0SPINT - 0xE002001C, S1SPINT - 0xE003001C) This register contains the interrupt flag for the SPI interface.

  • Page 186: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE The block diagram of the SPI solution implemented in SPI0 and SPI1 interfaces is shown in the Figure 34. MOSI_in MOSI_out MISO_in MISO_out SPI Shift Register SCK_in SCK_out SS_in SPI Clock Generator &...
  • Page 187 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 SPI Interface May 03, 2004...

  • Page 188: 14. Can Controllers And Acceptance Filter

    CAN CONTROLLERS Each CAN Controller has a register structure similar to the Philips SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32 bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter.

  • Page 189: Pin Description

    CAN Controller 1 Registers E004 8000 - 805F CAN Controller 2 Registers E004 C000 - C05F CAN Controller 3 Registers (LPC2194/2294 only) E005 0000 - 005F CAN Controller 4 Registers (LPC2194/2294 only) CAN CONTROLLER REGISTERS CAN block implements the registers shown in Table 123 and 124. More detailed descriptions follow.

  • Page 190: Table 123: Can1, Can2, Can3 And Can4 Controller Register Map

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 123: CAN Acceptance Filter and Central CAN Registers Name Description Access Reset Value Address LUTerr LUT Error Register 0xE003 C01C CANTxSR CAN Central Transmit Status Register 0x003F 3F00 0xE004 0000 CANRxSR...
  • Page 191 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 124: CAN1, CAN2, CAN3 and CAN4 Controller Register Map Generic CAN1 CAN2 CAN3 CAN4 Register Description Access Address & Address & Address & Address & Name Name Name Name Name 0xE004 403C...

  • Page 192: Table 124: Can Mode Register (Canmod - 0Xe00X X000)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Mode Register (CANMOD - 0xE00x x000) This register controls the basic operating mode of the CAN Controller. Bits not listed read as 0 and should be written as 0. See Table 124 for details on specific CAN channel register address.

  • Page 193: Table 125: Can Command Register (Cancmr - 0Xe00X X004)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Command Register (CANCMR - 0xE00x x004) Writing to this write-only register initiates an action. Bits not listed should be written as 0. Reading this register yields zeroes. See Table 124 for details on specific CAN channel register address.

  • Page 194: Table 126: Can Global Status Register (Cangsr - 0Xe00X X008)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Global Status Register (CANGSR - 0xE00x x008) This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not listed read as 0 and should be written as 0. See Table 124 for details on specific CAN channel register address.

  • Page 195: Table 127: Can Interrupt And Capture Register (Canicr - 0Xe00X X00C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 128: CAN Interrupt and Capture Register (CANICR - 0xE00x x00C) CANICR Name Function Reset Value RM Set 1: Receive Interrupt -- this bit is set whenever the RBS bit in CANSR and the RIE bit in CANIER are both 1, indicating that a received message is available.=.

  • Page 196: Table 128: Can Interrupt Enable Register (Canier - 0Xe00X X010)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 128: CAN Interrupt and Capture Register (CANICR - 0xE00x x00C) CANICR Name Function Reset Value RM Set Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field.

  • Page 197: Table 129: Can Bus Timing Register (Canbtr - 0Xe00X X014)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Bus Timing Register (CANBTR - 0xE00x x014) This register controls how various CAN timings are derived from the VPB clock. It can be read at any time, but can only be written if the RM bit in CANmod is 1.
  • Page 198 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 132: CAN Status Register (CANSR - 0xE00x x01C) CANSR Name Function Reset Value RM Set 4, 12, 20 These bits are identical to the RS bit in the GSR. TS1, 5, 13, 21 TS2, 1: The CAN Controller is transmitting a message from this Tx Buffer.

  • Page 199: Table 132: Can Rx Frame Status Register (Canrfs - 0Xe00X X020)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Rx Frame Status Register (CANRFS - 0xE00x x020) This register defines the characteristics of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 124 for details on specific CAN channel register address.

  • Page 200: Table 135: Can Rx Data Register 1 (Canrda - 0Xe00X X028)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Rx Data Register A (CANRDA - 0xE00x x028) This register contains the first 1-4 Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1. See Table 124 for details on specific CAN channel register address.

  • Page 201: Table 137: Can Tx Frame Information Register (Cantfi1, 2, 3 - 0Xe00X X030, 40, 50)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Tx Frame Information Register (CANTFI1, 2, 3 - 0xE00x x030, 40, 50) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer.

  • Page 202: Can Controller Operation

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Tx Data Register A (CANTDA1, 2, 3 - 0xE00x x038, 48, 58) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the first 1-4 Data bytes of the next transmit message.
  • Page 203 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Sleep Mode The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition.

  • Page 204: Centralized Can Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CENTRALIZED CAN REGISTERS Three read-only registers group the bits in the Status registers of the CAN controllers for common accessibility. If devices with more or fewer CAN controllers are defined, the number of bits used in the active bytes will change correspondingly. Each defined byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits.

  • Page 205: Global Acceptance Filter

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Central Miscellaneous Status Register (CANMSR - 0xE004 0008) Table 145: CAN Central Miscellaneous Status Register (CANMSR - 0xE004 0008) CANMSR Name Function Reset Value 1: one or both of the Tx and Rx Error Counters has reached the limit set in the EWL...

  • Page 206: Figure 37: Entry In Either Extended Identifier Table

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 If Extended (29-bit) Identifiers are used in the application, at least one of the other two tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers and one for ranges of Extended Identifiers. The table of individual Extended Identifiers must be arranged in ascending numerical order.

  • Page 207: Acceptance Filter Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ACCEPTANCE FILTER REGISTERS Acceptance Filter Mode Register (AFMR - 0xE003 C000) Table 146: Acceptance Filter Modes Register (AFMR - 0xE003 C000) AFMR Name Function Reset Value 1: if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are AccOff ignored.

  • Page 208: Table 148: Extended Frame Start Address Register (Eff_Sa - 0Xe003 C00C)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) Table 149: Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) EFF_sa Name Function Reset Value The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below.

  • Page 209: Examples Of Acceptance Filter Tables And Id Index Values

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 LUT Error Register (LUTerr - 0xE003 C01C) Table 153: LUT Error Register (LUTerr - 0xE003 C01C) LUTerr Name Function Reset Value This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM.

  • Page 210: Fullcan Mode

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Look-up Table RAM SFF_sa 0 d := 000 h := 0 0000 0000 b column_lower column_upper VPB BASE+ ID Index # Address 00d = 04d = 44d = 48d = 30h 52d =...

  • Page 211: Table 154: Format Of Automatically Stored Rx Message

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 1. The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two. SFF_sa must be rounded up to a multiple of 4 if necessary.
  • Page 212 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Start Read 1st word SEM == 01? This message has not been SEM == 11? received since last check. Clear SEM, write back 1st word Read 2nd and 3rd words Read 1st word...
  • Page 213 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CAN Controllers and Acceptance Filter May 03, 2004...

  • Page 214: 15. Timer0 And Timer1

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 15. TIMER0 AND TIMER1 Timer0 and Timer1 are functionally identical except for the peripheral base address. FEATURES • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.

  • Page 215: Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 DESCRIPTION The Timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

  • Page 216: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION Each Timer contains the registers shown in Table 157. More detailed descriptions follow. Table 157: TIMER0 and TIMER1 Register Map TIMER0 TIMER1 Generic Reset Description Access Address & Address &...
  • Page 217 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000) The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.

  • Page 218: Table 159: Match Control Register (Mcr: Timer0 - T0Mcr: 0Xe0004014; Timer1 - T1Mcr: 0Xe0008014)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Prescale Counter Register (PC: TIMER0 - T0PC: 0xE0004010; TIMER1 - T1PC: 0xE0008010) The 32-bit Prescale Counter controls division of pclk by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows.

  • Page 219: Table 160: Capture Control Register (Ccr: Timer0 - T0Ccr: 0Xe0004028; Timer1 - T1Ccr: 0Xe0008028)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.
  • Page 220 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 External Match Register (EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C) The External Match Register provides both control and status of the external match pins M(0-3). Table 162: External Match Register (EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C)

  • Page 221: Example Timer Operation

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 EXAMPLE TIMER OPERATION Figure 39 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value.

  • Page 222: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE The block diagram for TIMER0 and TIMER1 is shown in Figure 41. Match Register 0 Match Register 1 Match Register 2 Match Register 3 Match Control Register External Match Register Interrupt Register...
  • Page 223 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Timer0 and Timer1 May 03, 2004...

  • Page 224: Pulse Width Modulator (Pwm)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 16. PULSE WIDTH MODULATOR (PWM) LPC2119/2129/2194/2292/2294 Pulse Width Modulator is based on standard Timer 0/1 described in previous chapter. Application can choose among PWM and match functions available . FEATURES • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types.
  • Page 225 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.

  • Page 226: Figure 42: Pwm Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Match Register 0 Shadow Register 0 Load Enable Match Register 1 Shadow Register 1 Load Enable Match Register 2 Shadow Register 2 Load Enable Match Register 3 Shadow Register 3 Load Enable...

  • Page 227: Figure 43: Sample Pwm Waveforms

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 A sample of how PWM values relate to waveform outputs is shown in Figure 43. PWM output logic is shown in Figure 42 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The match register selections for various PWM outputs is shown in Table 164.
  • Page 228 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Rules for Single Edge Controlled PWM Outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high.

  • Page 229: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION Table 165 gives a brief summary of each of PWM related pins. Table 165: Pin summary Pin name Pin direction Pin Description PWM1 Output Output from PWM channel 1. PWM2 Output Output from PWM channel 2.

  • Page 230: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The PWM function adds new registers and registers bits as shown in Table 166 below. Table 166: Pulse Width Modulator Register Map Reset Name Description Access Address Value* PWM Interrupt Register. The IR can be written to clear interrupts. The IR can...
  • Page 231 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 166: Pulse Width Modulator Register Map Reset Name Description Access Address Value* PWM Match Register 5. MR5 can be enabled through MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt when it matches the TC.
  • Page 232 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PWM Interrupt Register (PWMIR - 0xE0014000) The PWM Interrupt Register consists of eleven bits (Table 167), seven for the match interrupts and four reserved for the future use. If an interrupt is generated then the corresponding bit in the PWMIR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt.
  • Page 233 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PWM Timer Control Register (PWMTCR - 0xE0014004) The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 168.
  • Page 234 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PWM Match Control Register (PWMMCR - 0xE0014014) The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter. The function of each of the bits is shown in Table 169.
  • Page 235 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 169: PWM Match Control Register (PWMMCR - 0xE0014014) Reset PWMMCR Function Description Value When one, the PWMTC and PWMPC will be stopped and PWMTCR[0] will be set to Stop on PWMMR5 0 if PWMMR5 matches the PWMTC.
  • Page 236 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PWM Latch Enable Register (PWMLER - 0xE0014050) ThePWM Latch Enable Register is used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is held in a shadow register.
  • Page 237 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Pulse Width Modulator (PWM) May 03, 2004...

  • Page 238: 17. A/D Converter

    Philips Semiconductors Preliminary User Manual LPC2119/2129/2194/2292/2294 ARM-based Microcontroller 17. A/D CONVERTER FEATURES • 10 bit successive approximation analog to digital converter. • Input multiplexing among 4 pins (LPC2119/2129/2194) or 8 pins (LPC2292/2294) • Power down mode • Measurement range 0 to 3 V •...
  • Page 239 Philips Semiconductors Preliminary User Manual LPC2119/2129/2194/2292/2294 ARM-based Microcontroller A/D Control Register (ADCR - 0xE0034000) Table 174: A/D Control Register (ADCR - 0xE0034000) ADCR Name Description Reset Value Selects which of the Ain3:0 (LPC2119/2129/2194) or Ain7:0 (LPC2292/2294) pins is (are) to be sampled and converted.

  • Page 240: Operation

    Philips Semiconductors Preliminary User Manual LPC2119/2129/2194/2292/2294 ARM-based Microcontroller A/D Data Register (ADDR - 0xE0034004) ADDR Name Description Reset Value This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read DONE and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
  • Page 241 Philips Semiconductors Preliminary User Manual LPC2119/2129/2194/2292/2294 ARM-based Microcontroller A/D Converter May 03, 2004...

  • Page 242: 18. Real Time Clock

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 18. REAL TIME CLOCK FEATURES • Measures the passage of time to maintain a calendar and clock. • Ultra Low Power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year.

  • Page 243: Architecture

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ARCHITECTURE clk32k Reference Clock Divider (Prescaler) Clock Generator Strobe Clk1 CCLK Time Comparators Alarm Counters Registers Counter Increment Counter Alarm Mask Enables Register Interrupt Enable Interrupt Generator Figure 44: RTC block diagram REGISTER DESCRIPTION The RTC includes a number of registers.
  • Page 244 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 176: Real Time Clock Register Map Reset Name Size Description Access Address Value Interrupt Location Register 0xE0024000 Clock Tick Counter. 0xE0024004 Clock Control Register 0xE0024008 CIIR Counter Increment Interrupt Register 0xE002400C...

  • Page 245: Rtc Interrupts

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 RTC INTERRUPTS Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register (AMR). Interrupts are generated only by the transition into the interrupt state. The ILR separately enables CIIR and AMR interrupts.

  • Page 246: Miscellaneous Register Group

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 MISCELLANEOUS REGISTER GROUP Table 177 summarizes the registers located from 0 to 7 of A[6:2]. More detailed descriptions follow. Table 177: Miscellaneous Registers Address Name Size Description Access Interrupt Location. Reading this location indicates the source of an 0xE0024000 interrupt.
  • Page 247 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Clock Control Register (CCR - 0xE0024008) The clock register is a 4-bit register that controls the operation of the clock divide circuit. Each bit of the clock register is described in Table 180.
  • Page 248 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 182: Alarm Mask Register Bits (AMR - 0xE0024010) Function Description AMRSEC When one, the Second value is not compared for the alarm. AMRMIN When one, the Minutes value is not compared for the alarm.

  • Page 249: Consolidated Time Registers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 CONSOLIDATED TIME REGISTERS The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32-bit values as shown in Tables 183, 184, and 185.
  • Page 250 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Consolidated Time Register 2 (CTIME2 - 0xE002401C) The Consolidate Time Register 2 contains just the Day of Year value. Table 185: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) CTIME2 Function Description...

  • Page 251: Time Counter Group

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 TIME COUNTER GROUP The time value consists of the eight counters shown in Tables 186 and 187. These counters can be read or written at the locations shown in Table 187. Table 186: Time Counter Relationships and Values...

  • Page 252: Alarm Register Group

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ALARM REGISTER GROUP The alarm registers are shown in Table 188. The values in these registers are compared with the time counters. If all the unmasked (See “Alarm Mask” on page 247.) alarm registers match their corresponding time counters then an interrupt is generated.

  • Page 253: Reference Clock Divider (Prescaler)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REFERENCE CLOCK DIVIDER (PRESCALER) The reference clock divider (hereafter referred to as the Prescaler) allows generation of a 32.768 kHz reference clock from any peripheral clock frequency greater than or equal to 65.536 kHz (2 x 32.768 kHz). This permits the RTC to always run at the proper rate regardless of the peripheral clock rate.

  • Page 254: Figure 45: Rtc Prescaler Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Example of Prescaler Usage In a simplistic case, the pclk frequency is 65.537 kHz. So: PREINT = int (pclk / 32768) - 1 = 1 and PREFRAC = pclk - ((PREINT +1) x 32768) = 1 With this prescaler setting, exactly 32,768 clocks per second will be provided to the RTC by counting 2 pclks 32,767 times, and 3 pclks once.
  • Page 255 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Prescaler Operation The Prescaler block labelled "Combination Logic" in Figure 45 determines when the decrement of the 13-bit PREINT counter is extended by one pclk. In order to both insert the correct number of longer cycles, and to distribute them evenly, the Combinatorial Logic associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter.

  • Page 256: 19. Watchdog

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 19. WATCHDOG FEATURES • Internally resets chip if not periodically reloaded • Debug mode • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled •...

  • Page 257: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The Watchdog contains 4 registers as shown in Table 193 below. Table 193: Watchdog Register Map Reset Name Description Access Address Value* Watchdog mode register. This register contains the basic mode and...
  • Page 258 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Watchdog Mode Register (WDMOD - 0xE0000000) The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits. WDEN WDRESET Debug/Operate without the Watchdog running Debug with the Watchdog interrupt but no WDRESET Operate with the Watchdog interrupt and WDRESET Once the WDEN and/or WDRESET bits are set they can not be cleared by software.

  • Page 259: Usage Notes On Watchdog Reset And External Start

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Watchdog Feed Register (WDFEED - 0xE0000008) Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer to the WDTC value. This operation will also start bit in the WDMOD register is not sufficient to the Watchdog if it is enabled via the WDMOD register.
  • Page 260 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Watchdog May 03, 2004...

  • Page 261: Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BLOCK DIAGRAM The block diagram of the Watchdog is shown below in the Figure 46. FEED ERROR FEED WDTC SEQUENCE FEED OK WDFEED UNDER FLOW 32-BIT DOWN pclk COUNTER ENABLE COUNT WDTV...

  • Page 262: 20. Flash Memory System And Programming

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 20. FLASH MEMORY SYSTEM AND PROGRAMMING This chapter describes the Flash Memory System and the Boot Loader. It also includes In-System Programming (ISP) and In- Application Programming (IAP) interfaces. FLASH MEMORY SYSTEM The Flash Memory System contains 16 sectors for 128 kB part and 17 sectors for 256 kB part.

  • Page 263: Figure 47: Map Of Lower Memory After Any Reset (128 Kb Flash Part)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 of the on-chip memory space i.e. the boot sector is also visible in the memory region starting from the address 0x7FFF E000. The flash boot loader is designed to run from this memory area but both the ISP and IAP software use parts of the on-chip RAM.
  • Page 264 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Communication Protocol All ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated ASCII strings.
  • Page 265 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 RAM used by ISP command handler ISP commands use on-chip RAM from 0x4000 0120 to 0x4000 01FF. The user could use this area, but the contents may be lost upon reset. Flash programming commands use the top 32 bytes of on-chip RAM. The stack is located at RAM top - 32. The maximum stack usage is 256 bytes and it grows downwards.

  • Page 266: Boot Process Flowchart

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BOOT PROCESS FLOWCHART Reset Initialize WatchDog Flag Set? User Code Valid? Enter ISP Mode? (P0.14 LOW?) Execute User code Run Auto-Baud Auto-Baud Successful? Receive crystal frequency Run ISP Command Handler Figure 48: Boot Process flowchart (Bootloader revisions before 1.61)

  • Page 267: Figure 49: Boot Process Flowchart (Bootloader Revisions 1.61 And Later)

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Reset Initialize Enabled? Enable Debug WatchDog Flag Set? Boot External? Enter ISP Mode? (P0.14 LOW?) User Code Valid? Enabled? Execute External Execute Internal User code User code Run Auto-Baud Auto-Baud Successful? Receive crystal...

  • Page 268: Sector Numbers

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 SECTOR NUMBERS Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicates the correspondence between sector numbers and memory addresses for LPC2119/2129/2194/2292/2294 device(s). IAP, ISP and RealMonitor routines are located in the Boot Sector.

  • Page 269: Code Read Protection

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 CODE READ PROTECTION This feature is available as of Bootloader revision 1.61. Code read protection is enabled by programming the flash address location 0x1FC (User flash sector 0) with value 0x87654321 (2271560481 Decimal). Address 0x1FC is used to allow some room for the fiq exception handler. When the code read protection is enabled the JTAG debug port, external memory boot and the following ISP commands are disabled: •...
  • Page 270 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ISP Commands The following commands are accepted by the ISP command handler. Detailed return codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
  • Page 271 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Set Baud Rate <Baud Rate> <stop bit> Table 200: ISP Set Baud Rate command description Command Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400 Input Stop bit: 1 | 2...
  • Page 272 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Write to RAM <start address> <number of bytes> The host should send the data only after receiving the CMD_SUCCESS return code. The host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data (before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines.
  • Page 273 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 204: ISP Read Memory command description Command Start Address: Address from where data bytes are to be read. This address should be a word Input boundary. Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.
  • Page 274 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. Table 205: ISP Prepare sector(s) for write operation command description Command...
  • Page 275 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Go <address> <Mode> Table 207: ISP Go command description Command Address: Flash or RAM address from which the code execution is to be started. This address should Input be on a word boundary.
  • Page 276 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Blank check sector(s) <start sector number> <end sector number> Table 209: ISP Blank check sector(s) command description Command Start Sector Number Input End Sector Number: Should be greater than or equal to start sector number.
  • Page 277 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Compare <address1> <address2> <number of bytes> Table 212: ISP Compare command description Command Address1(DST): Starting Flash or RAM address from where data bytes are to be compared. This address should be on word boundary.
  • Page 278 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 213: ISP Return Codes Summary Return Mnemonic Description Code Command is executed successfully. Sent by ISP CMD_SUCCESS handler only when command given by the host has been completely and successfully executed.
  • Page 279 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 IAP Commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1.
  • Page 280 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 0x7fffffb0 A rm_prefetchabort_handler 0x7fffffc0 A rm_dataabort_handler 0x7fffffd0 A rm_irqhandler 0x7fffffe0 A rm_irqhandler2 0x7ffffff0 T iap_entry As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively.

  • Page 281: Figure 50: Iap Parameter Passing

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Command Code Command Parameter 0 parameter table Parameter 1 ARM Register r0 ARM Register r1 Parameter n Status Code Command Result 0 result table Result 1 Result n Figure 50: IAP Parameter passing Prepare sector(s) for write operation This command makes flash write/erase operation a two step process.
  • Page 282 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Copy RAM to Flash Table 216: IAP Copy RAM to Flash command description Command Copy RAM to Flash Command code: 51 Param0(DST): Destination Flash address where data bytes are to be written. The destination address should be a 512 byte boundary.

  • Page 283: Table 217: Iap Blank Check Sector(S) Command Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Blank check sector(s) Table 218: IAP Blank check sector(s) command description Command Blank check sector(s) Command code: 53 Input Param0: Start Sector Number Param1: End Sector Number: Should be greater than or equal to start sector number.

  • Page 284: Table 220: Iap Compare Command Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Compare Table 221: IAP Compare command description Command Compare Command Code: 56 Param0(DST): Starting Flash or RAM address from where data bytes are to be compared. This address should be a word boundary.

  • Page 285: Jtag Flash Programming Interface

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 JTAG FLASH PROGRAMMING INTERFACE Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset. Flash Memory System and Programming...

  • Page 286: Embeddedice Logic

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 21. E ICE LOGIC MBEDDED FEATURES • No target resources are required by the software debugger in order to start the debugging session • Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly to the core •...

  • Page 287: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 PIN DESCRIPTION Table 223: EmbeddedICE Pin Description Pin Name Type Description Input Test Mode Select. The TMS pin selects the next state in the TAP state machine. Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It is a positive edge- Input triggered clock with the TMS and TCK signals that define the internal state of the device.

  • Page 288: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The EmbeddedICE logic contains 16 registers as shown in Table 224. below. The ARM7TDMI-S debug architecture is described in detail in "ARM7TDMI-S (rev 4) Technical Reference Manual" (ARM DDI 0234A) published by ARM Limited and is available via Internet at http://www.arm.com.

  • Page 289: Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BLOCK DIAGRAM The block diagram of the debug environment is shown below in Figure 51. JTAG PORT Serial/ Parallel EmbeddedICE Interface Interface EmbeddedICE Protocol Converter HOST RUNNING ARM7TDMI-S DEBUGGER TARGET BOARD Figure 51: EmbeddedICE Debug Environment Block Diagram...

  • Page 290: 22. Embedded Trace Macrocell

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 22. EMBEDDED TRACE MACROCELL FEATURES • Closely track the instructions that the ARM core is executing • 10 pin interface • 1 External trigger input • All registers are programmed through JTAG interface •...

  • Page 291: Pin Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Table 225: ETM Configuration Resource number/type Small External Outputs FIFOFULL Present Yes (Not wired) FIFO depth 10 bytes Trace Packet Width 1. For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)".

  • Page 292: Register Description

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REGISTER DESCRIPTION The ETM contains 29 registers as shown in Table 227. below. They are described in detail in the ARM IHI 0014E document published by ARM Limited, which is available via the Internet at http://www.arm.com.

  • Page 293: Block Diagram

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 BLOCK DIAGRAM The block diagram of the ETM debug environment is shown below in Figure 52. PERIPHERAL TRACE TRACE PORT ANALYZER TRIGGER PERIPHERAL CONNECTOR HOST JTAG RUNNING INTERFACE DEBUGGER EmbeddedICE UNIT CONNECTOR...

  • Page 294: 23. Realmonitor

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 23. REALMONITOR RealMonitor is a configurable software module which enables real time debug. RealMonitor is developed by ARM Inc. Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide (ARM DUI 0142A). It applies to a specific configuration of RealMonitor software programmed in the on-chip flash memory of this device.

  • Page 295: Figure 53: Realmonitor Components

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 RealMonitor Components As shown in Figure 53, RealMonitor is split in to two functional components: RMHost This is located between a debugger and a JTAG unit. The RMHost controller, , converts generic Remote Debug RealMonitor.dll...

  • Page 296: Figure 54: Realmonitor As A State Machine

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 How RealMonitor works In general terms, the RealMonitor operates as a state machine, as shown in Figure 54. RealMonitor switches between running and stopped states, in response to packets received by the host, or due to asynchronous events on the target. RMTarget supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at a time.
  • Page 297 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 • RealMonitor enters a loop, polling the DCC. If the DCC read buffer is full, control is passed to (RealMonitor rm_ReceiveData() internal function). If the DCC write buffer is free, control is passed to (RealMonitor internal function).

  • Page 298: How To Enable Realmonitor

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 HOW TO ENABLE REALMONITOR The following steps must be performed to enable RealMonitor. A code example which implements all the steps can be found at the end of this section. Adding stacks User must ensure that stacks are set up within application for each of the processor modes used by RealMonitor.
  • Page 299 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and user application. RealMonitor exception handling To function properly, RealMonitor must be able to intercept certain interrupts and exceptions. Figure 55 illustrates how exceptions can be claimed by RealMonitor itself, or shared between RealMonitor and application.
  • Page 300 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 RMTarget initialization While the processor is in a privileged mode, and IRQs are disabled, user must include a line of code within the start-up sequence of application to call rm_init_entry(). RealMonitor May 03, 2004...
  • Page 301 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 Code Example The following example shows how to setup stack, VIC, initialize RealMonitor and share non vectored interrupts: IMPORT rm_init_entry IMPORT rm_prefetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry ;Entry point of user application.
  • Page 302 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ; Initialize the IRQ mode stack for RealMonitor and User r1, r0, #0x1f r1, r1, #0x12 CPSR_c, r1 ;Keep 32 bytes for Abort mode stack SUB sp,r2,#0x7F ; Return to the original mode.
  • Page 303 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 ;MSR spsr, r12 ;Restore SPSR from r12 ;STMFD sp!, {r0} ;LDR r0, =VICBaseAddr ;STR r1, [r0,#VICVectAddrOffset] ;Acknowledge Non Vectored irq has finished ;LDMFD sp!, {r12,r14,r0} ;Restore registers ;SUBS pc, r14, #4 ;Return to the interrupted instruction ;user interrupt did not happen so call rm_irqhandler2.

  • Page 304: Realmonitor Build Options

    Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 REALMONITOR BUILD OPTIONS RealMonitor was built with the following options: RM_OPT_DATALOGGING=FALSE This option enables or disables support for any target-to-host packets sent on a non RealMonitor (third-party) channel. RM_OPT_STOPSTART=TRUE This option enables or disables support for all stop and start debugging features.
  • Page 305 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2194/2292/2294 "execute code" buffer size. Also refer to RM_OPT_EXECUTECODE option. RM_OPT_GATHER_STATISTICS=FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor. RM_DEBUG=FALSE This option enables or disables additional debugging and error-checking code in RealMonitor.
  • Page 306 Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

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