Usb Endpoint Interrupt Set Register (Usbepintset - 0Xe009 003C); Usb Endpoint Interrupt Priority Register (Usbepintpri - 0Xe009 0040) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1

14.7.10 USB Endpoint Interrupt Set register (USBEpIntSet - 0xE009 003C)

Writing a 1 to a bit in this register sets the corresponding bit in the endpoint interrupt
status register. Writing 0 will not have any impact. Each endpoint has its own bit in this
register. The USBEpIntSet is a write only register.
Table 191: USB Endpoint Interrupt Set register (USBEpIntSet - address 0xE009 003C) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol EP15TX
Bit 23
Symbol EP11TX
Bit 15
Symbol EP7TX
Bit 7
Symbol EP3TX
Table 192: USB Endpoint Interrupt Set register (USBEpIntSet - address 0xE009 003C) bit description
Bit Symbol Value
31:0 See 0
USBEpIntSet
1
bit allocation
table above

14.7.11 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xE009 0040)

This register determines whether the interrupt has to be routed to the fast interrupt line
(EP_FAST) or to the slow interrupt line (EP_SLOW). If set 1 the interrupt will be routed to
the fast interrupt bit of the device status register. Otherwise it will be routed to the slow
endpoint interrupt bit. Note that routing of multiple endpoints to EP_FAST or EP_SLOW is
possible. The Device Interrupt Priority register may override this register setting. Refer to
Section 14.7.6 "USB Device Interrupt Priority register (USBDevIntPri - 0xE009 002C)" on
page 203
Table 193: USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xE009 0040) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol EP15TX
9397 750 XXXXX
User manual
2. Issues 'Select Endpoint/Interrupt Clear' command for endpoint 10.
3. Waits for command to get processed and CDFULL bit to get set.
4. Now, endpoint status (for endpoint 10) is available in Command Data register (note
that hardware does not wait for the software to finish reading endpoint status in
Command Data register for endpoint 10).
5. Clears CDFULL bit again.
6. Issues 'Select Endpoint/Interrupt Clear' command for endpoint 5.
7. Waits for command to get processed and CDFULL bit to get set.
8. Now, endpoint status (for endpoint 5) is available in Command Data register for the
software to read.
30 29
EP15RX EP14TX
22 21
EP11RX EP10TX
14 13
EP7RX EP6TX
6 5
EP3RX EP2TX
Description
No effect.
Sets the corresponding bit in the Endpoint Interrupt Status register.
for more details. The USBEpIntPri is a write only register.
30 29
EP15RX EP14TX
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
28 27
EP14RX EP13TX
20 19
EP10RX EP9TX
12 11
EP6RX EP5TX
4 3
EP2RX EP1TX
28 27
E14RX EP13TX
UM10139
26 25
EP13RX EP12TX
18 17
EP9RX EP8TX
10 9
EP5RX EP4TX
2 1
EP1RX EP0TX
Reset value
0
26 25
EP13RX EP12TX
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
24
EP12RX
16
EP8RX
8
EP4RX
0
EP0RX
24
EP12RX
207