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Philips Semiconductors
Volume 1
3.6 Other system controls
Some aspects of controlling LPC2141/2/4/6/8 operation that do not fit into peripheral or
other registers are grouped here.
3.6.1 System Control and Status flags register (SCS - 0xE01F C1A0)
Table 13:
System Control and Status flags register (SCS - address 0xE01F C1A0) bit description
Bit
Symbol
Value
0
GPIO0M
0
1
1
GPIO1M
0
1
31:2
-
3.7 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
3.7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, the microcontroller will fetch an instruction
residing on the exception corresponding address as described in
vector locations" on page
will fill this table.
User manual
Description
GPIO port 0 mode selection.
GPIO port 0 is accessed via VPB addresses in a fashion compatible with previous
LCP2000 devices.
High speed GPIO is enabled on GPIO port 0, accessed via addresses in the on-chip
memory range. This mode includes the port masking feature described in the GPIO
chapter on page page 81.
GPIO port 1 mode selection.
GPIO port 1 is accessed via VPB addresses in a fashion compatible with previous
LCP2000 devices.
High speed GPIO is enabled on GPIO port 1, accessed via addresses in the on-chip
memory range. This mode includes the port masking feature described in the GPIO
chapter on page page 81.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
12. The MEMMAP register determines the source of data that
Rev. 01 — 15 August 2005
UM10139
Chapter 3: System Control Block
Table 3 "ARM exception
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0
0
NA
26
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