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Philips Semiconductors
Volume 1
Table 22:
PSEL Bits (PLLCFG bits [6:5])
00
01
10
11
Table 23:
MSEL Bits (PLLCFG bits [4:0])
00000
00001
00010
00011
...
11110
11111
3.8.11 PLL0 and PLL1 configuring examples
Example 1: an application not using the USB - configuring the PLL0
System design asks for F
Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently,
M - 1 = 5 will be written as PLLCFG[4:0].
Value for P can be derived from P = F
in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for
F
produces P = 2.67. The only solution for P that satisfies both of these requirements and is
listed in
Example 2: an application using the USB - configuring the PLL1
System design asks for F
Based on these specifications, M = 48 MHz / Fosc = 48 MHz / 12 MHz = 4. Consequently,
M - 1 = 3 will be written as PLLCFG[4:0].
Value for P can be derived from P = F
be in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for
F
criteria produces P = 3.33. Solution for P that satisfy both of these requirements and are
listed in
program PLLCFG[6:5] in the PLL1.
Example 2 has illustrated the way PLL1 should be configured. Since PLL0 and PLL1 are
independent, the PLL0 can be configured using the approach described in Example 1.
User manual
PLL Divider values
PLL Multiplier values
= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F
CCO
Table 22
is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.
= 156 MHz, P = 156 MHz / (2 x 48 MHz) = 1.625. The highest F
CCO
Table 22
are P = 2 and P = 3. Therefore, either of these two values can be used to
Rev. 01 — 15 August 2005
Value of P
1
2
4
8
Value of M
1
2
3
4
...
31
32
= 10 MHz and requires CCLK = 60 MHz.
OSC
/ (CCLK x 2), using condition that F
CCO
= 12 MHz and requires the USB clock of 48 MHz.
OSC
/ (48 MHz x 2), using condition that F
CCO
UM10139
Chapter 3: System Control Block
CCO
frequency criteria
CCO
frequency
CCO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
must be
must
CCO
34
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