Pll Frequency Calculation; Procedure For Determining Pll Settings - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1

3.8.9 PLL frequency calculation

The PLL equations use the following parameters:
Table 21:
Element
F
F
CCLK
M
P
The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M × F
The CCO frequency can be computed as:
F
The PLL inputs and settings must meet the following:

3.8.10 Procedure for determining PLL settings

If a particular application uses the PLL0, its configuration may be determined as follows:
Important: if a particular application is using the USB peripheral, the PLL1 must be
configured since this is the only available source of the 48 MHz clock required by
the USB. This limits the selection of F
User manual
Elements determining PLL's frequency
Description
the frequency from the crystal oscillator/external oscillator
OSC
the frequency of the PLL current controlled oscillator
CCO
the PLL output frequency (also the processor clock frequency)
PLL Multiplier value from the MSEL bits in the PLLCFG register
PLL Divider value from the PSEL bits in the PLLCFG register
or CCLK = F
OSC
= CCLK × 2 × P or F
CCO
•
F is in the range of 10 MHz to 25 MHz.
OSC
•
CCLK is in the range of 10 MHz to F
microcontroller - determined by the system microcontroller is embedded in).
•
F is in the range of 156 MHz to 320 MHz.
CCO
1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor (see
2. Choose an oscillator frequency (F
multiple of F .
OSC
3. Calculate the value of M to configure the MSEL bits. M = CCLK / F
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see
Table 23.
4. Find a value for P to configure the PSEL bits, such that F
frequency limits. F
CCO
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see
Rev. 01 — 15 August 2005
/ (2 × P)
CCO
× M × 2 × P
= F
CCO OSC
(the maximum allowed frequency for the
max
Section 3.11 "VPB divider" on page
). CCLK must be the whole (non-fractional)
OSC
is calculated using the equation given above. P must have one
to either 12 MHz, 16 MHz or 24 MHz.
OSC
UM10139
Chapter 3: System Control Block
40).
. M must be in
OSC
is within its defined
CCO
Table 22).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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