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Philips Semiconductors
Volume 1
13.4.8 SSP Masked Interrupt register (SSPMIS - 0xE006 801C)
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Table 170: SSP Masked Interrupt Status register (SSPMIS -address 0xE006 801C) bit
Bit
0
1
2
3
7:5
13.4.9 SSP Interrupt Clear Register (SSPICR - 0xE006 8020)
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPIMSC.
Table 171: SSP interrupt Clear Register (SSPICR - address 0xE006 8020) bit description
Bit
0
1
7:2
User manual
description
Symbol
Description
RORMIS
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
RTMIS
This bit is 1 when there is a Receive Timeout condition and
this interrupt is enabled. Note that a Receive Timeout can be
negated if further data is received.
RXMIS
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
TXMIS
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Symbol
Description
RORIC
Writing a 1 to this bit clears the "frame was received when
RxFIFO was full" interrupt.
RTIC
Writing a 1 to this bit clears the Receive Timeout interrupt.
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 15 August 2005
UM10139
Chapter 13: SSP
Reset value
0
0
0
0
NA
Reset value
NA
NA
NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
193
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