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Philips Semiconductors
Volume 1
17.4.1 A/D Control Register (AD0CR - 0xE003 4000 and AD1CR -
0xE006 0000)
Table 255: A/D Control Register (AD0CR - address 0xE003 4000 and AD1CR - address 0xE006 0000) bit description
Bit
Symbol
Value Description
7:0
SEL
15:8
CLKDIV
16
BURST
1
0
19:17 CLKS
000
001
010
011
100
101
110
111
20
-
21
PDN
1
0
23:22 -
User manual
Selects which of the AD0.7:0/AD1.7:0 pins is (are) to be sampled and converted. For
AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode,
only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8
ones. All zeroes is equivalent to 0x01.
The VPB clock (PCLK) is divided by (this value plus one) to produce the clock for the
A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should
program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but
in certain cases (such as a high-impedance analog source) a slower clock may be
desirable.
The AD converter does repeated conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that's in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
Conversions are software controlled and require 11 clocks.
This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the RESULT bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits).
11 clocks / 10 bits
10 clocks / 9bits
9 clocks / 8 bits
8 clocks / 7 bits
7 clocks / 6 bits
6 clocks / 5 bits
5 clocks / 4 bits
4 clocks / 3 bits
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The A/D converter is operational.
The A/D converter is in power-down mode.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Rev. 01 — 15 August 2005
UM10139
Chapter 17: A/D Converter
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0x01
0
0
000
NA
0
NA
267
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