Usb Dma Request Status Register (Usbdmarst - 0Xe009 0050); Usb Dma Request Clear Register (Usbdmarclr - 0Xe009 0054) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 205: USB Command Data register (USBCmdData - address 0xE009 0014) bit
Bit
7:0
31:8

14.8.11 USB DMA Request Status register (USBDMARSt - 0xE009 0050)

This register is set by the hardware whenever a packet (OUT) or token (IN) is received on
a realized endpoint. It serves as a flag for DMA engine to start the data transfer if the DMA
is enabled for this particular endpoint. Each endpoint has one reserved bit in this register.
Hardware sets this bit when a realized endpoint needs to be serviced through DMA.
Software can read the register content. DMA cannot be enabled for control endpoints
(EP0 and EP1). For easy readability the control endpoint is shown in the register contents.
The USBDMARSt is a read only register.
Table 206: USB DMA Request Status register (USBDMARSt - address 0xE009 0050) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol EP31
Bit 23
Symbol EP23
Bit 15
Symbol EP15
Bit 7
Symbol EP7
Table 207: USB DMA Request Status register (USBDMARSt - address 0xE009 0050) bit description
Bit Symbol Value
0 EP0 0
1 EP1 0
31:2 EPxx
0
1
[1]

14.8.12 USB DMA Request Clear register (USBDMARClr - 0xE009 0054)

Writing 1 into the register will clear the corresponding interrupt from the DMA Request
Status register. Writing 0 will not have any effect. Also, after a packet transfer, the
hardware clears the particular bit in DMA Request Status register. The USBDMARClr is a
write only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register
9397 750 XXXXX
User manual
description
Symbol Description
CommandData Command Data.
- Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
30 29
EP30 EP29
22 21
EP22 EP21
14 13
EP14 EP13
6 5
EP6 EP5
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0
bit must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit
must be 0).
≤ ≤
Endpoint xx (2 xx
DMA not requested by endpoint xx.
DMA requested by endpoint xx.
DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
Rev. 01 — 15 August 2005
28 27
EP28 EP27
20 19
EP20 EP19
12 11
EP12 EP11
4 3
EP4 EP3
31) DMA request.
UM10139
Chapter 14: USB Device Controller
26 25
EP26 EP25
18 17
EP18 EP17
10 9
EP10 EP9
2 1
EP2 EP1
(Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset value
0x00
NA
24
EP24
16
EP16
8
EP8
0
EP0
Reset value
0
0
0
206).
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