Page 1 UM10120 Volume 1: LPC213x User Manual Rev. 01 — 24 June 2005 User manual Document information Info Content Keywords LPC2131, LPC2132, LPC2134, LPC2136, LPC2138, LPC2000, LPC213x, ARM, ARM7, embedded, 32-bit, microcontroller Abstract An initial LPC213x User Manual revision...
Page 2 Date Description 20050624 Initial version Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 3: Chapter 1: General Information
C (400 kbit/s), SPI™ and SSP with buffering and variable data length capabilities. • Vectored interrupt controller with configurable priorities and vector addresses. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 4: Applications
UART1 with full modem interface LPC2136 32 kB 256 kB UART1 with full modem interface LPC2138 32 kB 512 kB UART1 with full modem interface © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 5: Architectural Overview
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 7: Block Diagram
WATCHDOG TIMER PWM6:1 PWM0 SYSTEM CONTROL 002aab067 (1) LPC2134/2136/2138 only. (2) LPC2132/2134/2136/2138 only. (3) Pins shared with GPIO. Fig 1. LPC2131/2/4/6/8 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 8: Chapter 2: Lpc2131/2/4/6/8 Memory Addressing
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2132) 0x0000 8000 0x0000 7FFF TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY 0.0 GB (LPC2131) 0x0000 0000 Fig 2. System memory map © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 9 VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 10 (AHB PERIPHERAL #3) 0xFFE0 C000 (AHB PERIPHERAL #2) 0xFFE0 8000 (AHB PERIPHERAL #1) 0xFFE0 4000 (AHB PERIPHERAL #0) 0xFFE0 0000 Fig 4. AHB peripheral map © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 11 (VPB PERIPHERAL #2) 0xE000 8000 TIMER0 (VPB PERIPHERAL #1) 0xE000 4000 WATCHDOG TIMER (VPB PERIPHERAL #0) 0xE000 0000 Fig 5. VPB peripheral map © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 12: Lpc2131/2132/2134/2136/2138 Memory Re-Mapping And Boot Block
Activated by a User Program as desired. Interrupt vectors are mode activation by re-mapped to the bottom of the Static RAM. User program © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 13: Memory Map Concepts And Operating Modes 12 Memory Re-Mapping
Details on re-mapping and examples can be found in Section 3.6 “Memory mapping control” on page © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 14 Note: Memory regions are not drawn to scale. Fig 6. Map of lower memory is showing re-mapped and re-mappable areas (LPC2138 with 512 kB Flash) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 15: Prefetch Abort And Data Abort Exceptions
This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 16: Chapter 3: System Control Block
More details on ISP and Serial Boot Loader can be found in "Flash Memory System and Programming" chapter on page 216. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 17: Register Description
Code Security Protection Register 0xE01F C184 Reset value relects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 18: Crystal Oscillator
Fig 7. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for C evaluation © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 19 MAX f = 30 MHz (Figure 7, mode a and/or b) (Figure 7, mode a) (Figure 7, mode b) Fig 8. F selection algorithm © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 20: External Interrupt Inputs
EXTINT register must be cleared! For details see Section 3.5.4 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” Section 3.5.5 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 21: External Interrupt Flag Register
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 22: Interrupt Wakeup Register
VICIntEnable register, and should write the corresponding 1 to the EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 23: External Interrupt Polarity Register (Extpolar - 0Xe01F C14C)
EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1). EXTPOLAR2 0 EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2). EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 24: Multiple External Interrupt Pins
ORed, the interrupt service routine can read the states of the pins from the GPIO port using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 25: Memory Mapping Control
Table 2 “ARM exception vector locations” on page 12. The MEMMAP register determines the source of data that will fill this table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 26: Memory Mapping Control Usage Notes
The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 27: Register Description
PLL operation. Reset value relects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 28: Pll Control Register (Pllcon - 0Xe01F C080)
(see Section 3.7.7 “PLL Feed register (PLLFEED - 0xE01F C08C)” Section 3.7.3 “PLL Configuration register (PLLCFG - 0xE01F C084)” on page 29). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 29: Pll Configuration Register (Pllcfg - 0Xe01F C084)
PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see Section 3.7.7 “PLL Feed register (PLLFEED - 0xE01F C08C)”). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 30: Pll Interrupt
PLLCON and PLLCFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLLFEED. 2. Write the value 0x55 to PLLFEED. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 31: Pll And Power-Down Mode
(the maximum allowed frequency for the microcontroller - determined by the system microcontroller is embedded in). • is in the range of 156 MHz to 320 MHz. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 32: Procedure For Detrmining Pll Settings
P = 2.67. The only solution for P that satisfies both of these requirements and is listed in Table 20 is P = 2. Therefore, PLLCFG[6:5] = 1 will be used. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 33: Power Control
The PCON register contains two bits. Writing a one to the corresponding bit causes entry to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 34: Power Control For Peripherals Register (Pconp - 0Xe01F Coc4)
Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 35: Power Control Usage Notes
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see description in Section 3.11 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 36 The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 37: Reset Source Identification Register (Rsir - 0Xe01F C180)
Assertion of the RESET signal sets this bit. Ths bit is cleared by POR, see text but is not affected by WDT or BOD reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 38: Vpb Divider
Reset value relects the data stored in used bits only. It does not include reserved bits content. 3.10.2 VPBDIV register (VPBDIV - 0xE01F C100) The VPB Divider register contains two bits, allowing three divider values, as shown in Table © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 39: Wakeup Timer
The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 40: Brown-Out Detection
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 41: Code Security Vs Debugging
Details on the way Code Read Protection works can be found in the "Flash Memory System and Programming" chapter on page 216. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 42: Introduction
If the same branch is taken again, the next instruction is taken from the Branch Trail Buffer. When a branch outside the contents of © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 43: Mam Blocks
Memory Address Flash Memory Bank ARM Local Bus INTERFACE BUFFERS Memory Data Fig 13. Simplified block diagram of the Memory Accelerator Module (MAM) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 44 Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 45 4.6 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 46 3 - MAM fetch cycles are 3 CCLKs in duration 4 - MAM fetch cycles are 4 CCLKs in duration 5 - MAM fetch cycles are 5 CCLKs in duration © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 47 20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 48 Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller (PL190) documentation. 5.3 Register description The VIC implements the registers shown in Table 33. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 49 0xFFFF F120 VICVectAddr9 Vector address 9 register. 0xFFFF F124 VICVectAddr10 Vector address 10 register. 0xFFFF F128 VICVectAddr11 Vector address 11 register. 0xFFFF F12C © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 50 Table 34: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit allocation Reset value: 0x0000 0000 Symbol Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 51 Writing a 1 clears the corresponding bit in the Software Interrupt r bit allocation register, thus releasing the forcing of this request. table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 52 Symbol Access Symbol I2C1 EINT3 EINT2 Access Symbol EINT1 EINT0 SPI1/SSP SPI0 I2C0 PWM0 Access Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 53 FIQ or IRQ. Table 44: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation Reset value: 0x0000 0000 Symbol Access © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 54 31:0 A bit read as 1 indicates a coresponding interrupt request being enabled, VICIRQStatus classified as IRQ, and asserted bit allocation table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 55 IRQ, and asserted. 31:6 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 56 The VIC registers can only be accessed in privileged mode. 31:1 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 57 0x0000 8000 External Interrupt 2 (EINT2) 0x0001 0000 External Interrupt 3 (EINT3) 0x0002 0000 ADC0 A/D Converter 0 end of conversion 0x0004 0000 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 58 Priority2 Vector interrupt 15 Priority14 VECTIRQ15 DEFAULT VECTORADDR VECTADDR15[31:0] [31:0] Priority15 nVICIRQIN VICVECTADDRIN[31:0] Fig 14. Block diagram of the Vectored Interrupt Controller (VIC) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 59 If an IRQ interrupt is received during execution of the MSR instruction, then the behavior will be as follows: • The IRQ interrupt is latched. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 60 LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 61 Therefore, if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 62 IRQ’s the following instruction could be placed at 0x0000 0018: LDR pc, [pc,#-0xFF0] This instruction loads PC with the address that is present in VICVectAddr register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 63 UART0 nor SPI0 have generated IRQ request but UART1 and/or I C were the reason, content of VICVectAddr will be identical to VICDefVectAddr. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 64 LPC2131 P0.25/AD0.4 P1.22/PIPESTAT1 P0.26/AD0.5 P0.13/MAT1.1 P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 002aab068 Fig 15. LPC2131 64-pin package © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 65 LPC2132 P0.25/AD0.4/AOUT P1.22/PIPESTAT1 P0.26/AD0.5 P0.13/MAT1.1 P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 002aab406 Fig 16. LPC2132 64-pin package © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 66 Fig 17. LPC2134/6/8 64-pin package 6.2 Pin description for LPC2131/2/4/6/8 Pin description for LPC2131/2/4/6/8 and a brief explanation of corresponding functions are shown in the following table. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 67 SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave PWM2 — Pulse Width Modulator output 2 EINT2 — External interrupt 2 input © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 68 EINT2 — External interrupt 2 input. AD1.5 — A/D converter 1, input 5. This analog input is always connected to its pin. Available in LPC2134/6/8 only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 69 P0.26 — General purpose digital input/output pin AD0.5 — A/D converter 0, input 5. This analog input is always connected to its pin. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 70 PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up. P1.22/ P1.22 — General purpose digital input/output pin PIPESTAT1 PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 71 RTC Power Supply: 3.3 V on this pin supplies the power to the RTC. Bidirectional pin; Plain input; 3 State Output; 10 ns Slew rate Control; TTL with Hysteresis; 5 V Tolerant. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 72 Bidirectional pin; Plain input; 3 State Output; 10 ns Slew rate Control; TTL with Hysteresis; Pull-up; 5 V Tolerant. Input; TTL with Hysteresis; 5 V Tolerant (pulses shorter than 20 ns are ignored). Analog like pads having ESD structures only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 73 Table 60 0xE002 C014 register 2. Reset value relects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 74 AD1.0 15:14 P0.7 GPIO Port 0.7 SSEL0 (SPI0) PWM2 EINT2 17:16 P0.8 GPIO Port 0.8 TXD UART1 PWM4 [1][2] Reserved or AD1.1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 75 The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 76 GPIO Port 0.23 Reserved Reserved Reserved 17:16 P0.24 Reserved Reserved Reserved Reserved 19:18 P0.25 GPIO Port 0.25 AD0.4 [2][3] Reserved or Aout(DAC) Reserved © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 77 0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution! © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 78 Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 79 0xE002 8000 0xE002 8010 state of the GPIO configured port pins can IO0PIN IO1PIN always be read from this register, regardless of pin direction. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 80 Reset value 31:0 P1xVAL GPIO pin value bits. Bit 0 in IO1PIN corresponds to P1.0 ... Bit 31 in IO1PIN Undefined corresponds to P1.31. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 81 This register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 82 Following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] and at the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]: IO0PIN = (IO0PIN && #0xFFFF00FF) || #0x0000A500 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 83 Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as they were before. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 84 UART0 contains registers organized as shown in Table 73. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 85 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 73: UART0 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
Page 86 UART0 Divisor Latches. Details on how to select the right value for U0DLL and U0DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 87 9.3.5 UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0) The U0IER is used to enable the three UART0 interrupt sources. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 88 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. FIFO Enable These bits are equivalent to U0FCR[0]. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 89 Section 9.3.6 “UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)” Section 9.3.2 “UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write Only)” © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 90 9.3.8 UART0 Line Control Register (U0LCR - 0xE000 C00C) The U0LCR determines the format of the data character that is to be transmitted or received. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 91 Note: A parity error is associated with the character at the top of the UART0 RBR FIFO. Parity error status is inactive. Parity error status is active. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 92 U0SCR has occurred. Table 85: UART0 Scratch pad register (U0SCR - address 0xE000 C01C) bit description Symbol Description Reset value A readable, writable byte. 0x00 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 93 Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 94 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 18. LPC2131/2/4/6/8 UART0 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 95 Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external modem. The complement value of this signal is stored in U1MCR[1]. LPC2134/6/8 only. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 96 UART1 contains registers organized as shown in Table 76. The Divisor Latch Access Bit (DLAB) iscontained in U1LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 97 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 88: UART1 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
Page 98 UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 99 10.3.5 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0) The U1IER is used to enable the four UART1 interrupt sources. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 100 Note that U1IIR[0] is active low. The pending Pending interrupt can be determined by evaluating U1IIR[3:1]. At least one interrupt is pending. No interrupt is pending. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 101 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 102 U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 10.3.7 UART1 FIFO Control Register (U1FCR - 0xE001 0008) The U1FCR controls the operation of the UART1 RX and TX FIFOs. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 103 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. Forced "1" stick parity. Forced "0" stick parity. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 104 U1LSR[0] is set when the U1RBR holds an unread character and is cleared when Ready the UART1 RBR FIFO is empty. (RDR) U1RBR is empty. U1RBR contains valid data. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 105 UART1 FIFO. U1RBR contains no UART1 RX errors or U1FCR[0]=0. UART1 RBR contains at least one UART1 RX error. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 106 As soon as TXEn becomes 0, UART1 transmittion will stop. Table 103 describes how to use TXEn bit in order to achieve software flow control. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 107 Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 108 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 19. LPC2131/2/4/6/8 UART1 block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 109 C-bus (see "The I C-bus specification" description under the heading "Fast-Mode", and notes for the table titled "Characteristics of the SDA and SCL I/O stages © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 111 C Data register (I2DAT), and then clear the SI bit. In this case, the data direction bit (R/W) should be 1 to indicate a read. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 112 C function. AA bit must be set to 1 to acknowledge its own slave address or the general call address. The STA, STO and SI bits are set to 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 113 A = Not acknowledge (SDA high) From Slave to Master S = START Condition P = STOP Condition Fig 25. Format of Slave Transmitter mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 114 Input signals are synchronized with the internal clock , and spikes shorter than three clocks are filtered out. The output for I C is a special pad designed to conform to the I C specification. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 115 CONTROL REGISTER & SCL DUTY I2CONCLR I2SCLH CYCLE REGISTERS I2SCLL STATUS STATUS Staus REGISTER DECODER I2STAT Fig 26. I C serial interface block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 116 C will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Fig 27. Arbitration procedure © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 117 C control register contains bits used to control the following I C block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 118 I C control register. Reset value relects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 119 START condition thereafter. If the I interface is in slave mode, an internal STOP condition is generated, but is not transmitted on the bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 120 C interrupt Clear bit. Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 121 - address 0xE005 C008) bit description Bit Symbol Description Reset value 7:0 Data This register holds data values that have been received, or are to be transmitted. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 122 0 through 400 kHz. Each register value must be greater than or equal to 4. Table 115 gives some examples of I C-bus rates based on PCLK frequency and I2SCLL and I2SCLH values. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 123 For each status code, the required software action and details of the following serial transfer are given in tables from Table 120 Table 124. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 124 121. After a repeated start condition (state 0x10), the I C block may switch to the master transmitter mode by loading I2DAT with SLA+W. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 125 AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 126 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 29. Format and States in the Master Transmitter mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 127 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 30. Format and States in the Master Receiver mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 128 This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 31. Format and States in the Slave Receiver mode © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 129 AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 130 C-bus will be released; not addressed SLA+R/W or Data slave will be entered. bytes. No I2DAT action A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 131 STOP condition will be transmitted; STO flag will be reset. Read data byte STOP condition followed by a START condition will be transmitted; STO flag will be reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 132 DATA byte has been Read data byte Data byte will be received and ACK will received; ACK has be returned. been returned. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 133 Own SLA will be recognized; General call address will be recognized if I2ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 134 Own SLA will be recognized; General call address will be recognized if I2ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 135 STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 136 In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 138 This section provides examples of operations that must be performed by various I C state service routines. This includes: • Initialization of the I C block after a Reset. • C Interrupt Service © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 139 11.9.2 Start Master Transmit function Begin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a Start. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 140 ACK bit will be received. 1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 141 1. Decrement the Master data counter, skip to step 5 if not the last data byte. 2. Write 0x14 to I2CONSET to set the STO and AA bits. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 142 1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 143 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 144 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 145 1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x24 to I2CONSET to set the STA and AA bits. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 146 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 147 SSEL signal. When CPHA = 1, the SSEL signal will always go inactive between data transfers. This is not guaranteed when CPHA = 0 (the signal can remain active). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 148 At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 149 6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 150 SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the status register will be activated. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 151 This signal is not directly driven by the master. It could be driven by a simple general purpose I/O under software control. On the LPC2131/2/4/6/8 (unlike earlier Philips ARM devices) the SSEL0 pin can be used for a different function when the SPI0 interface is only used in Master mode. For example, pin hosting the SSEL0 function can be configured as an output digital GPIO pin and used to select one of the SPI0 slaves.
Page 152 SCK is active high. SCK is active low. MSTR Master mode select. The SPI operates in Slave mode. The SPI operates in Master mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 153 Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 154 CCLK /VPB divider rate as determined by the VPBDIV register contents. 12.4.5 SPI Interrupt register (S0SPINT - 0xE002 001C) This register contains the interrupt flag for the SPI0 interface. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 155 GENERATOR & DETECTOR SPI Interrupt SPI REGISTER INTERFACE VPB Bus SPI STATE CONTROL SCK_OUT_EN MOSI_OUT_EN OUTPUT MISO_OUT_EN ENABLE LOGIC Fig 37. SPI block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 156 Any other time, the SSP either holds it in its inactive state, or does not drive it (leaves it in high impedance state). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 157 13.3.1 Texas Instruments Synchronous Serial (SSI) frame format Figure 38 shows the 4-wire Texas Instruments synchronous serial frame format supported by the SSP module. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 158 SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is placed on the CLK pin when data is not being transferred. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 159 SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 160 For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 162 13.3.8 Semiconductor Microwire frame format Figure 43 shows the Microwire frame format for a single frame. Figure 44 shows the same format when back-to-back frames are transmitted. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 164 Fig 45. Microwire frame format (continuos transfers) 13.4 Register description The SSP contains 9 registers as shown in Table 134. All registers are byte, half word and word accessible. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 165 14 bit transfer 1110 15 bit transfer 1111 16 bit transfer Frame Format. Microwire This combinationion is not supported and should not be used. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 166 (MISO). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 167 CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 168 This bit is 1 if the Tx FIFO is at least half empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 169 Writing a 1 to this bit clears the Receive Timeout interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 170 14.4 Pin description Table 144 gives a brief summary of each of the Timer/Counter related pins. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 171 MAT1.3 (2 pins) : P0.18 and P0.20 14.5 Register description Each Timer/Counter contains the registers shown in Table 145. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 172 Capture Register 1. See CR0 description. 0xE000 4030 0xE000 8030 T0CR1 T1CR1 Capture Register 2. See CR0 description. 0xE000 4034 0xE000 8034 T0CR2 T1CR2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 173 14.5.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 174 Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 175 Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 176 Reset on MR0: the TC will be reset if MR0 matches it. Feature disabled. MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. This interrupt is disabled © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 177 Capture on CAPn.3 rising edge: a sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC. This feature is disabled. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 178 15:12 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 179 TCR[0] (counter enable) Iterrupt Fig 47. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 180 MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER * Note: that the capture register 3 cannot be used on TIMER0 Fig 48. Timer block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 181 (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 182 PWM. The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 183 Note: this diagram is intended to clarify the function of the PWM rather than to suggest a specific design implementation. Fig 49. PWM block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 184 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 185 Output from PWM channel 6. 15.4 Register description The PWM function adds new registers and registers bits as shown in Table 155 below. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 186 PWMTC. In addition, a match between PWMMR5 and the PWMTC clears PWM5 in either single-edge mode or double-edge mode, and sets PWM6 if it is in double-edge mode. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 187 The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 157. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 188 Counter is reset on the next PCLK. This causes the PWM TC to increment on every PCLK when PWMPR = 0, every 2 PCLKs when PWMPR = 1, etc. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 189 PWMTC. This interrupt is disabled. PWMMR3R 1 Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. This feature is disabled © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 190 Selects single edge controlled mode for PWM2. PWMSEL3 Selects double edge controlled mode for the PWM3 output. Selects single edge controlled mode for PWM3. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 191 Write to the PWMLER, setting bits 1 and 2 at the same time. • The altered values will become effective at the next reset of the timer (when a PWM Match 0 event occurs). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 192 Control Register (PWMMCR - 0xE001 4014)”. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 193 Analog Power and Ground. These should be nominally the same voltages as V and V , but should be isolated to minimize noise and error. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 194 Important: START bits must be 000 when BURST = 1 or conversons will not start. Conversions are software controlled and require 11 clocks. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 195 Start conversion on a rising edge on the selected CAP/MAT signal. 31:28 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 196 Conversions are software controlled and require 11 clocks. 23:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 197 ADC readings. An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 198 350 µA. 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 199 A pin not exceeding 100 pF. A load impedance value greather than that value will cause settling time longer than the specified time. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 200 CLK1 CCLK TIME ALARM COMPARATORS COUNTERS REGISTERS COUNTER INCREMENT ALARM MASK Counter INTERRUPT ENABLE enables REGISTER INTERRUPT GENERATOR Fig 51. RTC block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 201 RTC is enabled. Reset value relects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 202 Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 203 If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler, as on earlier devices in the Philips Embedded ARM family. If this bit is 1, the CTC takes its clock from the 32 kHz oscillator that’s connected to the RTCX1 and RTCX2 pins (see Section 18.7 “RTC external 32 kHz...
Page 204 18.4.9 Consolidated Time register 0 (CTIME0 - 0xE002 4014) The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes, Hours, and Day of Week. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 205 The time value consists of the eight counters shown in Table 178 Table 179. These counters can be read or written at the locations shown in Table 179. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 206 The interrupt is cleared when a one is written to bit one of the Interrupt Location Register (ILR[1]). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 207 The result is not a continuous output at a constant frequency, some clock periods will be one PCLK longer than others. However, the overall result can always be 32,768 counts per second. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 208 With this prescaler setting, exactly 32,768 clocks per second will be provided to the RTC by counting 2 PCLKs 32,767 times, and 3 PCLKs once. In a more realistic case, the PCLK frequency is 10 MHz. Then, © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 209 Logic associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter. These associations are shown in the following Table 184. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 210 53. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected externally to the microcontroller. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 212 The Watchdog Time-Out Flag (WDTOF) can be examined to determine if the watchdog has caused the reset condition. The WDTOF flag must be cleared by software. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 213 Once the watchdog interrupt is serviced, it can be disabled in the VIC or the watchdog interrupt request will be generated indefinitely. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 214 Reset value 31:0 Count Counter timer value. 0x0000 00FF 19.5 Block diagram The block diagram of the Watchdog is shown below in the Figure © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 215 2. WDEN and WDRESET are sticky bits. Once set they can’t be cleared until the watchdog underflows or an external reset occurs. Fig 54. Watchdog block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 217 ASCII string ("Synchronized<CR><LF>") to the Host. In response to this host should send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 218 Data flow is resumed by sending the ASCII control character DC1 (start). The host should also support the same flow control scheme. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 219 The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. he user could use this area if RealMonitor based debug is not required. The Flash boot loader does not initialize the stack for RealMonitor. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 220 LPC2131/2/4/6/8 devices containing 32, 64, 128, 256 and 512K bytes of Flash respectively. IAP, ISP, and RealMonitor routines are located in the boot block. The © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 221 Secondly, it encodes data words to be written to the memory. The error correction capability consists of single bit error correction with Hamming code. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 222 ISP command can be given by the host. Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go" commands. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 223 CMD_SUCCESS return code. Example "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 224 If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>". In response the host should retransmit the bytes. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 225 "R 1073741824 4<CR><LF>" reads 4 bytes of data from address 0x4000 0000. 20.8.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 226 Example "C 0 1073774592 512<CR><LF>" copies 512 bytes from the RAM address 0x4000 8000 to the flash address 0. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 228 Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>. Description This command is used to read the boot code version number. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 229 Command to prepare sector for write operation was WRITE_OPERATION not executed. COMPARE_ERROR Source and destination data not equal. BUSY Flash programming hardware interface is busy. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 230 Define pointer to function type, which takes two parameters and returns void. Note the IAP returns the result with the base address of the table residing in R1. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 231 Blank check sector(s) Table 214 Read Part ID Table 215 Read Boot code version Table 216 Compare Table 217 Reinvoke ISP Table 218 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 232 Sector(s)" command causes relevant sectors to be protected again. The boot sector can not be prepared by this command. To prepare a single sector use the same "Start" and "End" sector numbers. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 233 The boot sector can not be erased by this command. To erase a single sector use the same "Start" and "End" sector numbers. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 234 Result0: 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)> Description This command is used to read the boot code version number. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 235 Destination address is not on a correct boundary. SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 236 Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 237 An example of this would be to set the first breakpoint to 1.For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual...
Page 238 GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 239 JTAG PORT Serial parallel EMBEDDEDICE interface EMBEDDED INTERFACE PROTOCOL CONVERTER Host running ARM7TDMI-S debugger TARGET BOARD Fig 58. EmbeddedICE debug environment block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 240 Table 222: ETM configuration Resource number/type Small Pairs of address comparators Data Comparators 0 (Data tracing is not supported) Memory Map Decoders Counters Sequencer Present © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 241 P1.20/TRACESYNC, and ensure that any external driver connected to P1.20/TRACESYNC is either driving high, or is in high-impedance state, during Reset. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 242 External Output 1 to 4 Holds the controlling events for each output. WO 110 10xx Reserved 110 11xx Reserved 111 0xxx Reserved 111 1xxx © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 243 CONNECTOR TRACE TRACE PORT ANALYZER TRIGGER PERIPHERAL PERIPHERAL CONNECTOR Host running JTAG debugger INTERFACE UNIT EMBEDDEDICE Fig 59. ETM debug environment block diagram © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 244 Multi-ICE must place the core into a debug state. While the processor is in this state, which can be millions of cycles, normal program execution is suspended, and interrupts cannot be serviced. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 245 It uses the EmbeddedICE logic, and communicates with the host using the DCC. For more details on RMTarget functionality, see the RealMonitor Target Integration Guide (ARM DUI 0142A). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 246 – Data and Prefetch aborts caused by user foreground application. This indicates an error in the application being debugged. In both cases the host is notified and the user application is stopped. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 247 A stack for this mode is always required. RealMonitor uses 12 words while processing an undefined instruction exception. 23.4.4 SVC mode RealMonitor makes no use of this stack. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 248 Interrupt Controller. The easiest way to do this is to write a branch instruction (<address>) into the vector table, where the target of the branch is the start address of the relevant RealMonitor exception handler. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 249 LDR pc, Reset_Address LDR pc, Undefined_Address LDR pc, SWI_Address LDR pc, Prefetch_Address LDR pc, Abort_Address NOP ; Insert User code valid signature here. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 250 ; Return to the original mode. CPSR_c, r0 ; Initialize the stack for user application ; Keep 256 bytes for IRQ mode stack sp,r2,#0x17F ; /********************************************************************* © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 251 ;Return to the interrupted instruction ;user interrupt did not happen so call rm_irqhandler2. This handler ;is not aware of the VIC interrupt priority hardware so trick © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 252 ARM debugger. Examples of such facilities include the keyboard input, screen output, and disk I/O. RM_OPT_SAVE_FIQ_REGISTERS=TRUE This option determines whether the FIQ-mode registers are saved into the registers block when RealMonitor stops. RM_OPT_READBYTES=TRUE © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 253 This option specifies whether RMTarget is built for interrupt-driven mode or polled mode. RM_FIFOSIZE=NA This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 254 UM10120 Philips Semiconductors Volume 1 Chapter 23: RealMonitor This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 255 Power-On Reset Pulse Width Modulator Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver/Transmitter Vector Interrupt Controller VLSI Peripheral Bus © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 256 Philips Semiconductors for any damages resulting from such application. 24.3Trademarks Right to make changes —...
Page 257 Table 30: Summary of MAM registers ....46 Table 55: Connection of interrupt sources to the Vectored continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 258 Table 81: UART0 interrupt handling ....89 Table 105:I2C0CONSET and I2C1CONSET used to continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 260 0xE002 4084) bit description ... . .208 Table 221:EmbeddedICE logic registers ... . 239 continued >> © Koninklijke Philips Electronics N.V. 2005. All rights reserved. User manual Rev. 01 — 24 June 2005...
Page 270 Trademarks......256 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Philips LPC213 Series User Manual

Chapter 1: General Information

Chapter 2: LPC2131/2/4/6/8 Memory Addressing

Chapter 3: System Control Block

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