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Philips Semiconductors
Volume 1
Table 249: PWM Timer Control Register (PWMTCR - address 0xE001 4004) bit description
Bit
0
1
2
3
7:4
16.4.3 PWM Timer Counter (PWMTC - 0xE001 4008)
The 32-bit PWM Timer Counter is incremented when the Prescale Counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the PWMTC will count up
through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event
does not cause an interrupt, but a Match register can be used to detect an overflow if
needed.
16.4.4 PWM Prescale Register (PWMPR - 0xE001 400C)
The 32-bit PWM Prescale Register specifies the maximum value for the PWM Prescale
Counter.
16.4.5 PWM Prescale Counter register (PWMPC - 0xE001 4010)
The 32-bit PWM Prescale Counter controls division of PCLK by some constant value
before it is applied to the PWM Timer Counter. This allows control of the relationship of the
resolution of the timer versus the maximum time before the timer overflows. The PWM
Prescale Counter is incremented on every PCLK. When it reaches the value stored in the
PWM Prescale Register, the PWM Timer Counter is incremented and the PWM Prescale
Counter is reset on the next PCLK. This causes the PWM TC to increment on every PCLK
when PWMPR = 0, every 2 PCLKs when PWMPR = 1, etc.
User manual
Symbol
Description
Counter Enable When one, the PWM Timer Counter and PWM Prescale
Counter are enabled for counting. When zero, the
counters are disabled.
Counter Reset
When one, the PWM Timer Counter and the PWM
Prescale Counter are synchronously reset on the next
positive edge of PCLK. The counters remain reset until
TCR[1] is returned to zero.
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
PWM Enable
When one, PWM mode is enabled. PWM mode causes
shadow registers to operate in connection with the
Match registers. A program write to a Match register will
not have an effect on the Match result until the
corresponding bit in PWMLER has been set, followed by
the occurrence of a PWM Match 0 event. Note that the
PWM Match register that determines the PWM rate
(PWM Match 0) must be set up prior to the PWM being
enabled. Otherwise a Match event will not occur to
cause shadow register contents to become effective.
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Rev. 01 — 15 August 2005
UM10139
Chapter 16: PWM
Reset value
0
0
NA
0
NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
260
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