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Philips Semiconductors
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Similarly, when a packet is successfully transferred to the host from any of IN
non-isochronous endpoint buffer, an interrupt is generated. When there is no data
available in any of the buffers (for a given IN non-isochronous endpoint), a data request
generates an interrupt only if Interrupt on NAK feature for that endpoint type is enabled
and existing interrupt is cleared. Upon receiving the interrupt, the software can load any
data to be sent using transmit length and data registers. For IN isochronous endpoints, the
data available in the buffer will be sent only if the buffer is validated; otherwise, an empty
packet will be sent. Like OUT isochronous endpoints, there will be no interrupt generated
specific to IN isochronous endpoints other than the frame interrupt.
14.5.4 DMA Mode Transfer (LPC2146/8 only)
Under DMA mode operation the USB device will act as a master on the AHB bus and
transfers the data directly from the memory to the endpoint buffer and vice versa. A duplex
channel DMA acts as a AHB master on the bus.
The endpoint 0 of USB (default control endpoint) will receive the setup packet. It will not
be efficient to transfer this data to the USB RAM since the CPU has to decode this
command and respond back to the host. So, this transfer will happen in the slave mode
only.
For each Isochronous endpoint, one packet transfer happens every frame. Hence, the
DMA transfer has to be synchronized to the frame interrupt.
The DMA engine also support Auto Transfer Length Extraction (ATLE) mode for bulk
transfers. In this mode the DMA engine recovers the transfer size from the incoming
packet stream.
14.6 Interfaces
14.6.1 Software Interface
The software interface of the USB device block consists of a register view and the format
definitions for the endpoint descriptors. These two aspects are addressed in the following
sections.
14.6.2 Register Map
The following registers are located in the AHB clock domain. The minimum AHB clock
frequency should be 18 MHz. They can be accessed directly by the CPU. All registers are
32 bit wide and aligned in the word address boundaries.
USB slave mode registers are located in the address region 0xE009 0000 to
0xE009 004C. All unused address in this region reads "DEADABBA".
DMA related registers are located in the address region 0xE009 0050 to 0xE009 00FC. All
unused address in this region reads invalid data.
9397 750 XXXXX
User manual
Rev. 01 — 15 August 2005
UM10139
Chapter 14: USB Device Controller
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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