Usb Endpoint Interrupt Clear Register (Usbepintclr - 0Xe009 0038) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 188: USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xE009 0034) bit description
Bit Symbol Value
31:0 See 0
USBEpIntEn
1
bit allocation
table above

14.7.9 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xE009 0038)

Writing a 1 to this bit clears the bit in the endpoint interrupt status register. Writing 0 will
not have any impact. When the endpoint interrupt is cleared from this register, the
hardware will clear the CDFULL bit in the Device Interrupt Status register. On completion
of this action, the CDFULL bit will be set and the Command Data register will have the
status of the endpoint. Endpoint Interrupt register and CDFULL bit of Device Interrupt
status register are related through clearing of interrupts in USB clock domain. Whenever
software attempts to clear a bit of Endpoint Interrupt register, hardware will clear CDFULL
bit before it starts issuing "Select Endpoint/Clear Interrupt" command (refer to
14.9.11 "Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)" on
page
will have to wait for CDFULL bit to be set to '1' (whenever it expects data from hardware)
before it can read Command Data register. Each physical endpoint has its own reserved
bit in this register. The bit field definition is the same as the Endpoint Interrupt Status
Register as shown in Table 172. The USBEpIntClr is a write only register.
Table 189: USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xE009 0038) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol EP15TX
Bit 23
Symbol EP11TX
Bit 15
Symbol EP7TX
Bit 7
Symbol EP3TX
Table 190: USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xE009 0038) bit description
Bit Symbol Value
31:0 See 0
USBEpIntClr
1
bit allocation
table above
Software is allowed to issue clear operation on multiple endpoints as well. Let us take an
example:
Assume bits 5 and 10 of Endpoint Interrupt Status register are to be cleared. The software
can issue Clear operation by writing in Endpoint Interrupt Clear register (with
corresponding bit positions set to '1'). Then hardware will do the following:
9397 750 XXXXX
User manual
Description
No effect.
The corresponding bit in the Endpoint Interrupt Status register
(Section 14.7.7) transfers its status to the Device Interrupt Status register
(Section 14.7.2). Having a bit in the USBEpIntEn set to 1 implies operating
in the slave mode.
229) and sets the same bit when command data is available for reading. Software
30 29
EP15RX EP14TX
22 21
EP11RX EP10TX
14 13
EP7RX EP6TX
6 5
EP3RX EP2TX
Description
No effect.
Clears the corresponding bit in the Endpoint Interrupt Status register.
1. Clears CDFULL bit of Device Interrupt Status register.
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
28 27
EP14RX EP13TX
20 19
EP10RX EP9TX
12 11
EP6RX EP5TX
4 3
EP2RX EP1TX
UM10139
Reset value
0
26 25
EP13RX EP12TX
18 17
EP9RX EP8TX
10 9
EP5RX EP4TX
2 1
EP1RX EP0TX
Reset value
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Section
24
EP12RX
16
EP8RX
8
EP4RX
0
EP0RX
206