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Philips LPC2101 User Manual

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UM10161
Volume 1: LPC2101/02/03 User Manual
Rev. 01 — 12 January 2006
Document information
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Content
Keywords
LPC2101, LPC2102, LPC2103, ARM, ARM7, embedded, 32-bit,
microcontroller
Abstract
An initial LPC2101/02/03 user manual revision
User manual

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  • Page 1 UM10161 Volume 1: LPC2101/02/03 User Manual Rev. 01 — 12 January 2006 User manual Document information Info Content Keywords LPC2101, LPC2102, LPC2103, ARM, ARM7, embedded, 32-bit, microcontroller Abstract An initial LPC2101/02/03 user manual revision...
  • Page 2 Date Description 20060112 Initial version Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 3: Chapter 1: General Information

    16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2101/02/03 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale.

  • Page 4: Applications

    UART1 with full modem interface 1.5 Architectural overview The LPC2101/02/03 consist of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the ARM Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)

  • Page 5: Arm7Tdmi-S Processor

    ARM website. 1.7 On-chip flash memory system The LPC2101/02/03 incorporate a 8 kB, 16 kB, and 32 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways: •...

  • Page 6: On-Chip Static Ram (Sram)

    1.8 On-chip Static RAM (SRAM) On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2/4/8 kB of static RAM respectively. The LPC2101/02/03 SRAM is designed to be accessed as a byte-addressed memory.

  • Page 7: Block Diagram

    GENERAL P0[31:0] REAL-TIME CLOCK RTXC2 PURPOSE I/O VBAT WATCHDOG SYSTEM CONTROL TIMER 002aab814 (1) Pins shared with GPIO. Fig 1. LPC2101/02/03 block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 8: Chapter 2: Lpc2101/02/03 Memory Addressing

    Chapter 2: LPC2101/02/03 Memory addressing Rev. 01 — 12 January 2006 User manual 2.1 Memory maps The LPC2101/02/03 incorporates several distinct memory regions, shown in the following figures. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset.
  • Page 9 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 10 (AHB PERIPHERAL #3) 0xFFE0 C000 (AHB PERIPHERAL #2) 0xFFE0 8000 (AHB PERIPHERAL #1) 0xFFE0 4000 (AHB PERIPHERAL #0) 0xFFE0 0000 Fig 4. AHB peripheral map © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 11 2.2 LPC2101/02/03 memory re-mapping and boot block 2.2.1 Memory map concepts and operating modes The basic concept on the LPC2101/02/03 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written.

  • Page 12: Memory Map Concepts And Operating Modes 11 Memory Re-Mapping

    1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 13: Prefetch Abort And Data Abort Exceptions

    32 kB Flash) 2.3 Prefetch abort and data abort exceptions The LPC2101/02/03 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are: •...
  • Page 14 UART0 space) may result in an access to the register defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the LPC2101/02/03 documentation and are not a supported feature. Note that the ARM core stores the Prefetch Abort flag along with the associated instruction (which will be meaningless) in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address.

  • Page 15: Chapter 3: System Control Block

    External Reset input - A LOW on this pin resets the chip, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 16: Register Description

    Section 3.8 “Phase Locked Loop (PLL)” on page 24 for details and frequency limitations. The onboard oscillator in the LPC2101/02/03 can operate in one of two modes: slave mode and oscillation mode. © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
  • Page 17 10 pF 18 pF, 18 pF < 220 Ω 20 pF 38 pF, 38 pF < 140 Ω 30 pF 58 pF, 58 pF © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 18: External Interrupt Inputs

    3.5 External interrupt inputs The LPC2101/02/03 includes up to three External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.

  • Page 19: Register Description

    The same goes for external interrupt handling. More details on power-down mode will be discussed in the following chapters. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 20: Interrupt Wake-Up Register (Intwake - 0Xe01F C144)

    When one, assertion of EINT0 will wake up the processor from Power-down mode. EXTWAKE1 When one, assertion of EINT1 will wake up the processor from Power-down mode. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 21: External Interrupt Mode Register (Extmode - 0Xe01F C148)

    VICIntEnable register, and should write the corresponding 1 to the EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear the EXTINT bit that could be set by changing the polarity. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 22: Other System Controls

    Figure 10 “Reset block diagram including the wake-up timer” on page 35 Fig 8. External interrupt logic 3.6 Other system controls Some aspects of controlling LPC2101/02/03 operation that do not fit into peripheral or other registers are grouped here. © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

  • Page 23: System Control And Status Flags Register (Scs - 0Xe01F C1A0)

    The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 24: Phase Locked Loop (Pll)

    The PLL is controlled by the registers shown in Table 15. More detailed descriptions follow. Warning: Improper setting of the PLL values may result in incorrect operation of the device! © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 25 PLL operation. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 26: Pll Control Register (Pllcon - 0Xe01F C080)

    (see Section 3.8.7 “PLL Feed register (PLLFEED - 0xE01F C08C)” Section 3.8.3 “PLL Configuration register (PLLCFG - 0xE01F C084)” on page 27). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 27: Pll Configuration Register (Pllcfg - 0Xe01F C084)

    PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see Section 3.8.7 “PLL Feed register (PLLFEED - 0xE01F C08C)”). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 28: Pll Interrupt

    Same as 00 combination. This prevents the possibility of the PLL being connected without also being enabled. The PLL is active and has been connected. CCLK/system clock is sourced from the PLL. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 29: Pll Feed Register (Pllfeed - 0Xe01F C08C)

    CCLK = F The CCO frequency can be computed as: = CCLK × 2 × P or F × M × 2 × P © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 30: Procedure For Determining Pll Settings

    3.8.11 PLL configuring examples Example: an application configuring the PLL System design asks for F = 10 MHz and requires CCLK = 60 MHz. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 31: Power Control

    P = 2. Therefore, PLLCFG[6:5] = 1 will be used. 3.9 Power control The LPC2101/02/03 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.

  • Page 32: Power Control Register (Pcon - 0Xe01F Coco)

    Important: valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register! © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 33: Power Control Usage Notes

    0. 3.10 Reset Reset has two sources on the LPC2101/02/03: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the wake-up timer (see description in Section 3.12 “Wake-up...
  • Page 34 The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 35: Reset Source Identification Register (Rsir - 0Xe01F C180)

    Reset. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 36: Apb Divider

    (the previous setting is retained). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 37: Wake-Up Timer

    The actual interrupt (if any) occurs after the wake-up timer expires, and is handled by the Vectored Interrupt Controller. However, the pin multiplexing on the LPC2101/02/03 (see Section 6.2 on page 61 Section 7.4 on page 66) was designed to allow other peripherals to bring the device out of Power-down mode.

  • Page 38: Code Security Vs. Debugging

    Applications in development typically need the debugging and tracing facilities in the LPC2101/02/03. Later in the life cycle of an application, it may be more important to protect the application code from observation by hostile or competitive eyes. The following feature of the LPC2101/02/03 allows an application to control whether it can be debugged or protected from observation.

  • Page 39: Introduction

    CPU fetch stalls. The LPC2101/02/03 uses one bank of Flash memory, compared to the two banks used on predecessor devices. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the Data Buffer.

  • Page 40: Mam Blocks

    4.3.1 Flash memory bank There is one bank of Flash memory with the LPC2101/02/03 MAM. Flash programming operations are not controlled by the MAM but are handled as a separate function. A “boot block” sector contains flash programming algorithms that may be called as part of the application program and a loader that may be run to allow serial programming of the flash memory.

  • Page 41: Flash Programming Issues

    In order to preclude the possibility of stale data being read from the Flash memory, the LPC2101/02/03 MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation. Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed.

  • Page 42: Mam Configuration

    Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 43: Mam Timing Register (Mamtim - 0Xe01F C004)

    20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 44: Chapter 5: Vectored Interrupt Controller (Vic)

    Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller (PL190) documentation. 5.3 Register description The VIC implements the registers shown in Table 35. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 45 0xFFFF F120 VICVectAddr9 Vector address 9 register. 0xFFFF F124 VICVectAddr10 Vector address 10 register. 0xFFFF F128 VICVectAddr11 Vector address 11 register. 0xFFFF F12C © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 46: Vic Registers

    Table 36: Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit allocation Reset value: 0x0000 0000 Symbol TIMER3 TIMER2 Access © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 47: Software Interrupt Clear Register (Vicsoftintclear - 0Xffff F01C)

    Writing a 1 clears the corresponding bit in the Software Interrupt r bit allocation register, thus releasing the forcing of this request. table. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 48: Raw Interrupt Status Register

    Symbol TIMER3 TIMER2 Access Symbol I2C1 EINT2 Access Symbol EINT1 EINT0 SSP/SPI1 SPI0 I2C0 Access Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 Access © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 49: Interrupt Enable Register

    FIQ or IRQ. Table 46: Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit allocation Reset value: 0x0000 0000 Symbol TIMER3 TIMER2 Access © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 50: Irq Status Register (Vicirqstatus -

    31:0 A bit read as 1 indicates a corresponding interrupt request being enabled, VICIRQStatus classified as IRQ, and asserted bit allocation table. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 51: Fiq Status Register (Vicfiqstatus - 0Xffff F004)

    IRQ, and asserted. 31:6 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 52: Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C)

    The VIC registers can only be accessed in privileged mode. 31:1 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 53: Interrupt Sources

    0x0000 8000 External Interrupt 2 (EINT2) 0x0001 0000 Reserved 0x0002 0000 A/D Converter 0 end of conversion 0x0004 0000 SI (state change) 0x0008 0000 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 54 15 priority14 DEFAULT VECTIRQ15 VECTORADDR VECTADDR15[31:0] [31:0] priority15 nVICIRQIN VICVECTADDRIN[31:0] Fig 13. Block diagram of the Vectored Interrupt Controller (VIC) © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 55: Spurious Interrupts

    Spurious interrupts are possible in the ARM7TDMI based microcontrollers such as the LPC2101/02/03 due to asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC state is changed between the moments when the core detects an interrupt, and the core actually processes an interrupt, problems may be generated.

  • Page 56: Workaround

    LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt will remain pending since we haven’t ; acknowledged it and will be reissued when interrupts © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 57: Solution 2: Disable Irqs And Fiqs Using Separate Writes To The Cpsr

    Therefore, if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 58 IRQ’s the following instruction could be placed at 0x0000 0018: LDR pc, [pc,#-0xFF0] This instruction loads PC with the address that is present in VICVectAddr register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 59 UART0 nor SPI0 have generated IRQ request but UART1 and/or I C were the reason, content of VICVectAddr will be identical to VICDefVectAddr. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 60: Table Of Contents

    P0.10/RTS1/CAP1.0/AD0.3 P0.21/SSEL1/MAT3.0 P0.24/AD0.2 VBAT P0.23/AD0.1 P0.22/AD0.0 DD(1V8) LPC2101/2102/2103 P0.9/RXD1/MAT2.2 P0.27/TRST/CAP2.0 P0.8/TXD1/MAT2.1 P0.28/TMS/CAP2.1 P0.7/SSEL0/MAT2.0 P0.29/TCK/CAP2.2 DBGSEL RTCK RTXC2 002aab821 Fig 14. LQFP48 pin configuration © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 61: Pin Description For Lpc2101/02/03

    P0.29/TCK/CAP2.2 P0.7/SSEL0/MAT2.0 DBGSEL RTXC2 002aab920 Fig 15. PLCC44 pin configuration 6.2 Pin description for LPC2101/02/03 Pin description for LPC2101/02/03 and a brief explanation of corresponding functions are shown in the following table. Table 58: Pin description Symbol LQFP48 PLCC44 Type Description P0.0 to P0.31...
  • Page 62 MAT1.0/AD0.5 DSR1 — Data Set Ready input for UART1. MAT1.0 — PWM output for Timer 1, channel 0. AD0.5 — Analog Input 5. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 63 P0.24 — General purpose Input/output digital pin (GPIO). AD0.2 — Analog Input 2. P0.25/AD0.6 P0.25 — General purpose Input/output digital pin (GPIO). AD0.6 — Analog Input 6. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 64: Vbat

    RTC power supply: 3.3 V on this pin supplies the power to the RTC. 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 65 3 ns. When configured as an ADC input, digital section of the pad is disabled. Pad provides special analog functionality. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 66: Features

    0x0000 0000 0xE002 C004 register 1. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 67: Pin Function Select Register 0 (Pinsel0 - 0Xe002 C000)

    Reserved 15:14 P0.7 GPIO Port 0.7 SSEL0 (SPI0) MAT2.0 (Timer 2) Reserved 17:16 P0.8 GPIO Port 0.8 TXD1 (UART1) MAT2.1 (Timer 2) Reserved © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 68: Pin Function Select Register 1 (Pinsel1 - 0Xe002 C004)

    Pin function select register 1 (PINSEL1 - 0xE002 C004) PINSEL1 Pin Name Value Function Value after reset P0.16 GPIO Port 0.16 EINT0 MAT0.2 (Timer 0) Reserved © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 69 P0.24 GPIO Port 0.24 Reserved Reserved AD0.2 19:18 P0.25 GPIO Port 0.25 Reserved Reserved AD0.6 21:20 P0.26 GPIO Port 0.26 Reserved Reserved AD0.7 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 70: Pin Function Select Register Values

    Details for a specific derivative may be found in the appropriate data sheet. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 71: Features

    General purpose input/output. The number of GPIOs actually available depends on the Output use of alternate functions. 8.4 Register description LPC2101/02/03 has one 32-bit General Purpose I/O port. A total of 32 input/output pins are available on PORT0. PORT0 is controlled by the registers shown in Table 64 Table...

  • Page 72: Koninklijke Philips Electronics N.v. 2006. All Rights Reserved

    Table 65 represent the enhanced GPIO features available on the LPC2101/02/03. All of these registers are located directly on the local bus of the CPU for the fastest possible read and write timing. An additional feature has been added that provides byte addressability of all GPIO registers.

  • Page 73: Gpio Port 0 Direction Register (Iodir, Port 0: Io0Dir - 0Xe002 8008; Fiodir, Port 0: Fio0Dir - 0X3Fff C000)

    Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30. 0x0000 0000 Controlled pin is input. Controlled pin is output. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 74: Fast Gpio Port 0 Mask Register (Fiomask, Port 0: Fio0Mask - 0X3Fff C010)

    Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN registers. When the FIOPIN register is read, this bit will not be updated with the state of the physical pin. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 75: Gpio Port 0 Pin Value Register (Iopin, Port 0: Io0Pin - 0Xe002 8000; Fiopin, Port 0: Fio0Pin - 0X3Fff C014)

    Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”) will be correlated to the current content of the Fast GPIO port pin value register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 76: Gpio Port 0 Output Set Register (Ioset, Port 0: Io0Set - 0Xe002 8004; Fioset, Port 0: Fio0Set - 0X3Fff C018)

    Access to a port pins via the FIOSET register is conditioned by the corresponding FIOMASK register (see Section 8.4.2 “Fast GPIO port 0 Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010)”). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 77: Gpio Port 0 Output Clear Register (Ioclr, Port 0: Io0Clr - 0Xe002 800C; Fioclr, Port 0: Fio0Clr - 0X3Fff C01C)

    Slow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit 0x0000 0000 31 in IO0CLR corresponds to P0.31. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 78: Gpio Usage Notes

    LOW (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to IO0SET), and the final write to IO0CLR register sets pin P0.7 back to LOW level. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 79: Example 2: An Immediate Output Of 0S And 1S On A Gpio Port

    GPIO pin is 3.5 times faster via the fast GPIO registers than it is when the legacy set of registers is used. As a result of the access speed increase, the © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 80: User Manual

    Figure 16 illustrates the code from above executed from the LPC2101/02/03 Flash memory. The PLL generated F =60 MHz out of external F = 12 MHz. The MAM CCLK was fully enabled with MEMCR = 2 and MEMTIM = 3, and APBDIV = 1 (PCLK = CCLK).

  • Page 81: User Manual

    Chapter 8: GPIO Fig 16. Illustration of the fast and slow GPIO access and output showing 3.5 x increase of the pin output frequency © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 82: Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (Uart0)

    UART0 contains registers organized as shown in Table 81. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 83 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 81: UART0 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...

  • Page 84: Uart0 Receiver Buffer Register (U0Rbr - 0Xe000 C000, When Dlab = 0, Read Only)

    (DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches. Details on how to select the right value for U0DLL and U0DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 85: Uart0 Fractional Divider Register (U0Fdr - 0Xe000 C028)

    The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 15 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 86: Uart0 Baudrate Calculation

    0.0640 9/(9+1) 0.0000 2000 0271 0.0000 1/(1+0) 0.0000 2400 0209 0.0320 12/(12+13) 0.0000 3600 015B 0.0640 5/(5+2) 0.0064 4800 0104 0.1600 12/(12+13) 0.0000 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 87: Uart0 Interrupt Enable Register (U0Ier - 0Xe000 C004, When Dlab = 0)

    Enable the RX line status interrupts. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 88: Uart0 Interrupt Identification Register (U0Iir - 0Xe000 C008, Read Only)

    The U0IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 89: User Manual

    These initialization conditions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 90: Uart0 Fifo Control Register

    Value Description Reset value Word Length 5 bit character length Select 6 bit character length 7 bit character length 8 bit character length © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 91: Uart0 Line Status Register

    Note: A parity error is associated with the character at the top of the UART0 RBR FIFO. Parity error status is inactive. Parity error status is active. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 92: Uart0 Scratch Pad Register

    U0SCR has occurred. Table 94: UART0 Scratch Pad Register (U0SCR - address 0xE000 C01C) bit description Symbol Description Reset value A readable, writable byte. 0x00 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 93: Uart0 Auto-Baud Control Register

    In mode 1 the baud-rate is measured between the falling edge and the subsequent rising edge of the UART0 Rx pin (the length of the start bit). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 94: Uart0 Transmit Enable Register

    × 9.3.14 UART0 Transmit Enable Register (U0TER - 0xE000 C030) LPC2101/02/03’s U0TER enables implementation of software flow control. When TXEn=1, UART0 transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART0 transmission will stop.

  • Page 95: Auto-Baud Modes

    After setting the U0DLM/U0DLL the end of auto-baud interrupt U0IIR ABEOInt will be set, if enabled. The U0RSR will now continue receiving the remaining bits of the ”A/a" character. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 96: Architecture

    U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 97: User Manual

    Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 98: User Manual

    RXD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 18. UART0 block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 99: Features

    UART1 contains registers organized as shown in Table 76. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 100 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 98: UART1 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...

  • Page 101: Uart1 Divisor Latch Registers 0 And 1 (U1Dll - 0Xe001 0000 And U1Dlm - 0Xe001 0004, When

    (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to select the right value for U1DLL and U1DLM can be found later on in this chapter. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 102: Uart1 Fractional Divider Register (U1Fdr - 0Xe001 0028)

    The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL ≤ 15 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 103: Uart1 Baudrate Calculation

    0.0640 9/(9+1) 0.0000 2000 0271 0.0000 1/(1+0) 0.0000 2400 0209 0.0320 12/(12+13) 0.0000 3600 015B 0.0640 5/(5+2) 0.0064 4800 0104 0.1600 12/(12+13) 0.0000 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 104: Uart1 Interrupt Enable Register (U1Ier - 0Xe001 0004, When Dlab = 0)

    U1IER[3] enables the modem interrupt. The status Status of this interrupt can be read from U1MSR[3:0]. Interrupt Disable the modem interrupt. Enable Enable the modem interrupt. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 105: Uart1 Interrupt Identification Register (U1Iir - 0Xe001 0008, Read Only)

    Note that U1IIR[0] is active LOWLOW. The pending Pending interrupt can be determined by evaluating U1IIR[3:1]. At least one interrupt is pending. No interrupt is pending. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 106: User Manual

    10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 107: Uart1 Fifo Control Register (U1Fcr - 0Xe001 0008)

    U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 10.3.8 UART1 FIFO Control Register (U1FCR - 0xE001 0008) The U1FCR controls the operation of the UART1 RX and TX FIFOs. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 108: Uart1 Line Control Register (U1Lcr - 0Xe001 000C)

    Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. Forced "1" stick parity. Forced "0" stick parity. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 109: Uart1 Modem Control Register (U1Mcr - 0Xe001 0010)

    UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted. Auto-RTS © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 110: User Manual

    Delta DCD or Modem Status Status (U1MCR[7]) Enable (U1MSR[0]) Trailing Edge RI or Interrupt Interrupt (U1IER[7]) Delta DSR (U1IER[3]) (U1MSR[3] or U1MSR[2] or (U1MSR[1])) © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 111: Uart1 Line Status Register (U1Lsr - 0Xe001 0014, Read Only)

    UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. Overrun error status is inactive. Overrun error status is active. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 112: Uart1 Modem Status Register (U1Msr - 0Xe001 0018)

    U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct affect on UART1 operation, they facilitate software implementation of modem signal operations. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 113: Uart1 Scratch Pad Register (U1Scr - 0Xe001 001C)

    This bit is automatically cleared after auto-baud completion. Auto-baud stop (auto-baud is not running). Auto-baud start (auto-baud is running).Auto-baud run bit. This bit is automatically cleared after auto-baud completion. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 114: Auto-Baud

    The auto-baud interrupts have to be cleared by setting the corresponding U1ACR ABTOIntClr and ABEOIntEn bits. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 115: Auto-Baud Modes

    After setting the U1DLM/U1DLL the end of auto-baud interrupt U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the remaining bits of the ”A/a" character. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 116: Uart1 Transmit Enable Register (U1Ter - 0Xe001 0030)

    Fig 21. Autobaud a) mode 0 and b) mode 1 waveform 10.3.17 UART1 Transmit Enable Register (U1TER - 0xE001 0030) LPC2101/02/03’s U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available.

  • Page 117: Architecture

    Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 118: User Manual

    RXD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE PD[7:0] DDIS INTERFACE PCLK Fig 22. UART1 block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 119: Chapter 11: I 2 C Interfaces I 2 C0 And I 2 C1

    C interfaces comply with entire I C specification, supporting the ability to turn power off to the LPC2101/02/03 without causing a problem with other devices on the same C-bus (see "The I C-bus specification" description under the heading "Fast-Mode". This ©...

  • Page 120: Pin Description

    The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 121: Master Receiver Mode

    For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer to Table 134. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 122: Slave Receiver Mode

    After the address and direction bit have been received, the SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to Table 135 for the status codes and actions. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 123: Slave Transmitter Mode

    11.6.1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 124: User Manual

    CONTROL REGISTER & SCL DUTY I2CONCLR CYCLE REGISTERS I2SCLH I2SCLL STATUS status STATUS REGISTER DECODER I2STAT Fig 29. I C serial interface block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 125: Address Register, I2Addr

    C will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Fig 30. Arbitration procedure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 126: Serial Clock Generator

    C-bus status. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 127: Control Register, I2Conset And I2Conclr

    I2C0ADR I2C1ADR and is not used in master mode. The least significant bit determines whether a slave responds to the general call address. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 128: C Control Set Register (I2Conset: I2C0, I2C0Conset - 0Xe001 C000 And I2C1, I2C1Conset - 0Xe005 C000)

    C interface to enter master mode and transmit a START condition or transmit a repeated START condition if it is already in master mode. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 129: User Manual

    C is in the master receiver mode. 2. A data byte has been received while the I C is in the addressed slave receiver mode. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 130: I 2 C Control Clear Register

    C states. When any of these states entered, the SI bit will be set. For a complete list of status codes, refer to tables from Table 133 Table 136. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 131: I 2 C Data Register

    I2SCLL defines the number of PCLK cycles for the SCL low time. The frequency is determined by the following formula (PCLK is the frequency of the peripheral bus APB): © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 132: Details Of I C Operating Modes

    Table 129: Abbreviations used to describe an I C operation Abbreviation Explanation Start Condition 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 133: Master Transmitter Mode

    After a repeated start condition (state 0x10). The I C block may switch to the master receiver mode by loading I2DAT with SLA+R). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 134: Master Receiver Mode

    I C block is in the master mode (see status 0x68 and 0x78). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 135: User Manual

    AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 136: User Manual

    This number (contained in I2STA) corresponds to a defined state of the C bus Fig 32. Format and states in the Master Transmitter mode © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 137: User Manual

    This number (contained in I2STA) corresponds to a defined state of the I C bus Fig 33. Format and states in the Master Receiver mode © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 138: User Manual

    This number (contained in I2STA) corresponds to a defined state of the C bus Fig 34. Format and states in the Slave Receiver mode © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 139: Slave Transmitter Mode

    AA. This means that the AA bit may be used to temporarily isolate the I C block from the I C-bus. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 140: User Manual

    C-bus will be released; not addressed SLA+R/W or Data slave will be entered. bytes. No I2DAT action A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 141: User Manual

    STOP condition will be transmitted; STO flag will be reset. Read data byte STOP condition followed by a START condition will be transmitted; STO flag will be reset. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 142: User Manual

    DATA byte has been Read data byte Data byte will be received and ACK will received; ACK has be returned. been returned. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 143: User Manual

    Own SLA will be recognized; General call address will be recognized if I2ADR[0] = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 144: User Manual

    Own SLA will be recognized; General call address will be recognized if I2ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 145: Miscellaneous States

    STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 146: Some Special Cases

    In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 147: C-Bus Obstructed By A Low Level On Scl Or Sda

    Table 137. OTHER MASTER DATA CONTINUES other Master sends retry repeated START earlier Fig 36. Simultaneous repeated START conditions from two masters © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 148: C State Service Routines

    (for master modes) is defined by loading CR0 and CR1 in I2CON. The master routines must be started in the main program. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 149: C Interrupt Service

    11.9.3 Start Master Receive function Begin a Master Receive operation by setting up the buffer, pointer, and data count, then initiating a Start. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 150: I 2 C Interrupt Routine

    1. Write Slave Address with R/W bit to I2DAT. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 151: Master Transmitter States

    1. Write 0x14 to I2CONSET to set the STO and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 152: State: 0X38

    Stop condition will be transmitted. 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 153: Slave Receiver States

    2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 154: State: 0X80

    Data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 155: Slave Transmitter States

    2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit. 11.9.9.5 State: 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 156: User Manual

    C interfaces 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 157: Chapter 12: Spi Interface (Spi0)

    SSEL signal. When CPHA = 1, the SSEL signal will always go inactive between data transfers. This is not guaranteed when CPHA = 0 (the signal can remain active). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 158: User Manual

    At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 159: General Information

    6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 160: Slave Operation

    SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the status register will be activated. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 161: Mode Fault

    This signal is not directly driven by the master. It could be driven by a simple general purpose I/O under software control. On the LPC2101/02/03 the SSEL0 pin can be used for a different function when the SPI0 interface is only used in Master mode. For example, the pin hosting the SSEL0 function can be configured as an output digital GPIO pin or used to select one of the Match outputs.

  • Page 162: Spi Control Register (S0Spcr - 0Xe002 0000)

    LSB First controls which direction each byte is shifted when transferred. SPI data is transferred MSB (bit 7) first. SPI data is transferred LSB (bit 0) first. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 163: Spi Status Register (S0Spsr - 0Xe002 0004)

    SPI data register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 164: Spi Data Register (S0Spdr - 0Xe002 0008) 164 Spi Clock Counter Register (S0Spccr - 0Xe002 000C)

    12.5 Architecture The block diagram of the SPI solution implemented in SPI0 interface is shown in the Figure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 165: User Manual

    GENERATOR & DETECTOR SPI Interrupt SPI REGISTER INTERFACE APB Bus SPI STATE CONTROL SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN OUTPUT ENABLE LOGIC Fig 40. SPI block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 166: Chapter 13: Ssp Controller (Spi1)

    Any other time, the SSP either holds it in its inactive state, or does not drive it (leaves it in HIGH impedance state). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 167: Bus Description

    13.3.1 Texas Instruments Synchronous Serial (SSI) frame format Figure 41 show the 4-wire Texas Instruments synchronous serial frame format supported by the SSP module. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 168: Spi Frame Format

    SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state HIGH value is placed on the CLK pin when data is not being transferred. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 169: Spi Format With Cpol=0,Cpha=0

    SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on the rising and propagated on the falling edges of the SCK signal. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 170: Spi Format With Cpol=0,Cpha=1

    For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 171: Spi Format With Cpol = 1,Cpha = 0

    HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 172: Spi Format With Cpol = 1,Cpha = 1

    13.3.8 Semiconductor Microwire frame format Figure 46 shows the Microwire frame format for a single frame. Figure 47 shows the same format when back-to-back frames are transmitted. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 173: User Manual

    SK, after the LSB of the frame has been latched into the SSP. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 174: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode

    Fig 48. Microwire frame format (continuos transfers) - details 13.4 Register description The SSP contains 9 registers as shown in Table 147. All registers are byte, half word and word accessible. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 175: Ssp Control Register 0 (Sspcr0 - 0Xe006 8000)

    14 bit transfer 1110 15 bit transfer 1111 16 bit transfer Frame Format. Microwire This combination is not supported and should not be used. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 176: Ssp Control Register 1 (Sspcr1 - 0Xe006 8004)

    (MISO). Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 177: Ssp Data Register

    CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 178: Ssp Interrupt Mask Set/Clear Register

    This bit is 1 if the Tx FIFO is at least half empty. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 179: Ssp Masked Interrupt Register (Sspmis - 0Xe006 801C)

    Writing a 1 to this bit clears the Receive Timeout interrupt. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 180: Features

    Analog Power and Ground. These should be nominally the same voltages as V and V but should be isolated to minimize noise and error. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 181: Register Description

    AD0DR7 channel 7. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 182: A/D Control Register (Ad0Cr - 0Xe003 4000)

    The A/D converter is in power-down mode. 23:22 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 183: A/D Global Data Register (Ad0Gdr - 0Xe003 4004)

    ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 184: A/D Status Register (Adstat, Adc0: Ad0Cr - 0Xe003 4004)

    Completion of a conversion on ADC channel 1 will not generate an interrupt. Completion of a conversion on ADC channel 1 will generate an interrupt. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 185: A/D Data Registers (Addr0 To Addr7, Adc0: Ad0Dr0 To Ad0Dr7 - 0Xe003 4010 To 0Xe003 402C)

    DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 186: Operation

    ADC readings. An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 187: Chapter 15: Timer/Counter Timer0 And Timer1

    Due to the limited number of pins on the LPC2101/02/03, only three of the Capture Inputs and three of the Match Ouputs of Timer 0 are connected to device pins.

  • Page 188: Pin Description

    MAT1.1: P0.13 • MAT1.2: P0.19 • MAT1.3: P0.20 15.5 Register description Each Timer/Counter contains the registers shown in Table 165. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 189: User Manual

    T0CR2 T1CR2 Capture Register 3. See CR0 description. 0xE000 4038 0xE000 8038 Note: CAP0.3 not available on Timer 0 T0CR3 T1CR3 Not usable © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 190: Interrupt Register (Ir, Timer0: T0Ir - 0Xe000 4000 And Timer1: T1Ir - 0Xe000 8000)

    15.5.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 191: Count Control Register (Ctcr, Timer0: T0Ctcr - 0Xe000 4070 And Timer1: T1Tcr - 0Xe000 8070)

    Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 192: Timer Counter (Tc, Timer0: T0Tc - 0Xe000 4008 And Timer1: T1Tc - 0Xe000 8008)

    Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 193: Match Control Register (Mcr, Timer0: T0Mcr - 0Xe000 4014 And Timer1: T1Mcr - 0Xe000 8014)

    Feature disabled. 15:12 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 194: Capture Registers (Cr0 - Cr3)

    Capture on CAPn.3 rising edge: A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC This feature is disabled. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 195: External Match Register (Emr, Timer0: T0Emr - 0Xe000 403C; And Timer1: T1Emr - 0Xe000 803C)

    EMC1 External Match Control 1. Determines the functionality of External Match 1. Table 172 shows the encoding of these bits. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 196: Pwm Control Register (Pwmcon, Timer0: Pwm0Con - 0Xe000 4074 And Timer1: Pwm1Con - 0Xe000 8074)

    MATn.3 is not pinned out on Timer0. 4:32 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 197: Rules For Single Edge Controlled Pwm Ouputs

    2 and the match register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt indicating that a match occurred is generated. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 198: Architecture

    Fig 51. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled 15.7 Architecture The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in Figure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 199: User Manual

    TIMER CONTROL REGISTER PRESCALE REGISTER (1) The capture register 3 (CAP0.3) is not available on TIMER0. Fig 52. Timer0/1 block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 200: Features

    Due to the limited number of pins on the LPC2101/02/03, none of the Capture Inputs of Timer3, only three of the Capture Inputs of Timer2, three of the Match Ouputs of Timer2, and four of the Match Outputs of Timer3 are connected to device pins.

  • Page 201: Pin Description

    MAT3.1: P0.13 • MAT3.2: P0.14 • MAT3.3: P0.15 16.5 Register description Each Timer/Counter contains the registers shown in Table 175. More detailed descriptions follow. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 202: User Manual

    Note: CAP3.1 not usable on Timer 3 T2CR1 T3CR1 Capture Register 2. See CR0 description. 0xE007 0034 0xE007 4034 Note: CAP3.2 not usable on Timer 3 T2CR2 T3CR2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 203: Interrupt Register (Ir Timer2: T2Ir -

    16.5.2 Timer Control Register (TCR, TIMER2: T2TCR - 0xE007 0004 and TIMER3: T3TCR - 0xE007 4004) The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 204: User Manual

    Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 205: Timer Counter (Tc, Timer2: T2Tc - 0Xe007 0008 And Timer3: T3Tc - 0Xe007 4008)

    Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 206: Match Control Register (Mcr, Timer2: T2Mcr - 0Xe007 0014 And Timer3: T3Mcr - 0Xe007 4014)

    Feature disabled. 15:12 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 207: Capture Registers (Cr0 - Cr3)

    Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. On TIMER2/3, CAPn.3 is disabled and values for CAP3RE, CAP3FE, and CAP3I are not defined. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 208: External Match Register (Emr, Timer2: T2Emr - 0Xe007 003C; And Timer3: T3Emr - 0Xe007 403C)

    Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). Toggle the corresponding External Match bit/output. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 209: Pwm Control Register (Pwmcon, Timer0: Pwm0Con - 0Xe007 0074 And Timer1: Pwm1Con - 0Xe007 4074)

    5. If a match register is set to zero, then the PWM output will go to HIGH at the first time the timer reaches its reset value and will stay HIGH continuously. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 210: Example Timer Operation

    Fig 54. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 211: Architecture

    Fig 55. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled 16.9 Architecture The block diagram for TIMER/COUNTER2 and TIMER/COUNTER3 is shown in Figure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 212: User Manual

    PRESCALE COUNTER MAXVAL reset enable TIMER CONTROL REGISTER PRESCALE REGISTER (1) The capture registers are not available on TIMER3. Fig 56. Timer2/3 block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 213: Chapter 17: Real Time Clock

    It uses little power in Power-down mode. On the LPC2101/02/03, the RTC can be clocked by a separate 32.768 KHz oscillator or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V...

  • Page 214: Register Description

    RTC is enabled. Reset value reflects the data stored in used bits only. It does not include reserved bits content. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 215: Rtc Interrupts

    Writing a zero has no effect. This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 216: Clock Tick Counter Register (Ctc - 0Xe002 4004)

    If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler, as on earlier devices in the Philips Embedded ARM family. If this bit is 1, the CTC takes its clock from the 32 kHz oscillator that’s connected to the RTCX1 and RTCX2 pins (see Section 17.7 “RTC external 32 kHz...

  • Page 217: Alarm Mask Register (Amr - 0Xe002 4010)

    17.4.9 Consolidated Time register 0 (CTIME0 - 0xE002 4014) The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes, Hours, and Day of Week. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 218: Consolidated Time Register 1 (Ctime1 - 0Xe002 4018)

    The time value consists of the eight counters shown in Table 194 Table 195. These counters can be read or written at the locations shown in Table 195. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 219: Leap Year Calculation

    The interrupt is cleared when a one is written to bit one of the Interrupt Location Register (ILR[1]). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 220: Rtc Usage Notes

    (external battery). If VBAT is not connected, the VBAT pin has to be pulled high or remain open. No provision is made in the LPC2101/02/03 to retain RTC status upon the VBAT power loss, or to maintain time incrementation if the clock source is lost, interrupted, or altered.

  • Page 221: Prescaler Integer Register (Preint - 0Xe002 4080)

    The reference clock divider consists of a 13-bit integer counter and a 15-bit fractional counter. The reasons for these counter sizes are as follows: 1. For frequencies that are expected to be supported by the LPC2101/02/03, a 13-bit integer counter is required. This can be calculated as 160 MHz divided by 32,768 minus 1 = 4881 with a remainder of 26,624.

  • Page 222: Prescaler Operation

    Logic associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter. These associations are shown in the following Table 200. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 223: Rtc External 32 Khz Oscillator Component Selection

    59. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected externally to the microcontroller. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 224: User Manual

    < 100 kΩ 18 pF, 18 pF 13 pF < 100 kΩ 22 pF, 22 pF 15 pF < 100 kΩ 27 pF, 27 pF © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 225: Chapter 18: Watchdog Timer (Wdt)

    The Watchdog Time-Out Flag (WDTOF) can be examined to determine if the watchdog has caused the reset condition. The WDTOF flag must be cleared by software. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 226: Register Description

    Once the watchdog interrupt is serviced, it can be disabled in the VIC or the watchdog interrupt request will be generated indefinitely. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 227: Watchdog Timer Constant Register (Wdtc - 0Xe000 0004)

    Reset value 31:0 Count Counter timer value. 0x0000 00FF 18.5 Block diagram The block diagram of the Watchdog is shown below in the Figure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 228: User Manual

    (2) WDEN and WDRESET are sticky bits. Once set they can’t be cleared until the watchdog underflows or an external reset occurs. Fig 60. Watchdog block diagram © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 229: Chapter 19: Flash Memory System And Programming

    RAM usage is described later in this chapter. The interrupt vectors residing in the boot block of the on-chip flash memory also become active after reset, i.e., the bottom 64 bytes © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 230: Criterion For Valid User Code

    "OK<CR><LF>" string is sent to the host. Host should respond by sending the crystal frequency (in kHz) at which the part is running. For example, if the part is running at 10 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 231: Communication Protocol

    Data flow is resumed by sending the ASCII control character DC1 (start). The host should also support the same flow control scheme. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 232: Isp Command Abort

    The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. he user could use this area if RealMonitor based debug is not required. The Flash boot loader does not initialize the stack for RealMonitor. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 233: Boot Process Flowchart

    Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC2101/02/03 devices containing 8, 16, and 32 kB of Flash respectively. IAP, ISP, and RealMonitor routines are located in the boot block. The boot block is present ©...

  • Page 234: Flash Content Protection Mechanism

    0x0000 7000 - 0x0000 7FFF 19.6 Flash content protection mechanism The LPC2101/02/03/8 is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold. Firstly, it decodes data words read from the memory into output data words. Secondly, it encodes data words to be written to the memory.

  • Page 235: Code Read Protection (Crp)

    Erase sector(s) E <start sector number> <end sector number> Table 219 Blank check sector(s) I <start sector number> <end sector number> Table 220 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 236: Unlock

    Table 212: Correlation between possible ISP baudrates and external crystal frequency (in MHz) ISP Baudrate vs. 9600 19200 38400 57600 115200 230400 External Crystal Frequency 10.0000 11.0592 12.2880 14.7456 15.3600 18.4320 19.6608 24.5760 25.0000 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 237: Echo

    The host should compare it with the checksum of the received bytes. If the check-sum matches then the host should respond with © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 238: Prepare Sector(S) For Write Operation

    To prepare a single sector use the same "Start" and "End" sector numbers. Example "P 0 0<CR><LF>" prepares the flash sector 0. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 239: Copy Ram To Flash

    This command is blocked when code read protection is enabled. Example "G 0 A<CR><LF>" branches to address 0x0000 0000 in ARM mode. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 240: Erase Sector(S)

    This command is used to read the part identification number. Table 222: LPC2101/02/03 part identification numbers Device ASCII/dec coding Hex coding LPC2103 327441 0x0004 FF11 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 241: Read Boot Code Version Number

    Count value is taken in to consideration where applicable. DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 242: Iap Commands

    #define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP command table and result table to the IAP function: unsigned long command[5]; © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 243: User Manual

    RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 244: Prepare Sector(S) For Write Operation

    Prepare sector(s) for write operation Input Command code: 50 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 245: Count_Error

    The boot sector can not be written by this command. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 246: Sector_Not_Blank

    Result0: Part Identification Number (see Table 222 “LPC2101/02/03 part identification numbers” on page 240 for details) Description This command is used to read the part identification number. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 247: Compare_Error

    Another option is to disable the PLL before making this IAP call. Important: TIMER1 registers must be programmed with reset values before "Reinvoke ISP" command is used. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 248: Iap Status Codes

    Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 249: Chapter 20: Embeddedice Logic

    An example of this would be to set the first breakpoint to 1.For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 250: Pin Description

    0072A)". Also used during entry into debug mode. 20.5 Reset state of multiplexed pins On the LPC2101/02/03, the pins TMS, TCK, TDI, TDO, AND TRST are multiplexed with P0.27 - P0.31. To have them come up as a Debug port, connect a weak bias resistor (4.7-10 kΩ...

  • Page 251: Register Description

    Watchpoint 1 Control Mask Holds watchpoint 1 control mask 10101 20.7 Block diagram The block diagram of the debug environment is shown below in Figure © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 252: Debug Mode

    66). RTCK may be driven HIGH externally or allowed to float HIGH via its on-chip pull-up. The RTCK output driver is disabled until the internal wake-up time has expired, © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 253: Jtag Pin Selection

    66). If at least one of the DBGSEL or RTCK lines is LOW at reset, JTAG will not be enabled and can not be used for later debugging. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 254: Chapter 21: Realmonitor

    Multi-ICE must place the core into a debug state. While the processor is in this state, which can be millions of cycles, normal program execution is suspended, and interrupts cannot be serviced. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 255: Realmonitor Components

    It uses the EmbeddedICE logic, and communicates with the host using the DCC. For more details on RMTarget functionality, see the RealMonitor Target Integration Guide (ARM DUI 0142A). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 256: How Realmonitor Works

    – Data and Prefetch aborts caused by user foreground application. This indicates an error in the application being debugged. In both cases the host is notified and the user application is stopped. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 257: How To Enable Realmonitor

    A stack for this mode is always required. RealMonitor uses 12 words while processing an undefined instruction exception. 21.4.4 SVC mode RealMonitor makes no use of this stack. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 258: Prefetch Abort Mode

    Interrupt Controller. The easiest way to do this is to write a branch instruction (<address>) into the vector table, where the target of the branch is the start address of the relevant RealMonitor exception handler. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 259: Rmtarget Initialization

    ;Define exception table. Instruct linker to place code at address 0x0000 0000 AREA exception_table, CODE LDR pc, Reset_Address LDR pc, Undefined_Address LDR pc, SWI_Address LDR pc, Prefetch_Address LDR pc, Abort_Address © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 260: User Manual

    ; Return to the original mode. CPSR_c, r0 ; Initialize the stack for user application ; Keep 256 bytes for IRQ mode stack sp,r2,#0x17F © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 261: User Manual

    ;user interrupt did not happen so call rm_irqhandler2. This handler ;is not aware of the VIC interrupt priority hardware so trick ;rm_irqhandler2 to return here © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 262: Realmonitor Build Options

    ARM debugger. Examples of such facilities include the keyboard input, screen output, and disk I/O. RM_OPT_SAVE_FIQ_REGISTERS=TRUE This option determines whether the FIQ-mode registers are saved into the registers block when RealMonitor stops. RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 263: User Manual

    This option specifies whether RMTarget is built for interrupt-driven mode or polled mode. RM_FIFOSIZE=NA This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 264: User Manual

    UM10161 Philips Semiconductors Volume 1 Chapter 21: RealMonitor This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 265: User Manual

    Phase-Locked Loop Pulse Width Modulator Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver/Transmitter Vector Interrupt Controller ARM Peripheral Bus © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 266: User Manual

    22.4 Tables Table 1: LPC2101/02/03 device information...4 Table 27: Reset Source identification Register (RSIR - Table 2: APB peripheries and base addresses .

  • Page 267: User Manual

    Only) bit description ....101 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 268: User Manual

    ......130 0xE006 8004) bit description ... . . 176 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 269: User Manual

    Table 197:Reference clock divider registers ..221 Table 173:PWM Control Register (PWMCON, TIMER0: Table 198:Prescaler Integer register (PREINT - address continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 270: Fig 14. Lqfp48 Pin Configuration

    Fig 1. LPC2101/02/03 block diagram....7 Fig 15. PLCC44 pin configuration ....61 Fig 2.

  • Page 271: User Manual

    Fig 58. RTC prescaler block diagram....222 Fig 59. RTC 32 kHz crystal oscillator circuit ..224 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 272: User Manual

    Operation ......39 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 273: User Manual

    0xFFFF F200-23C) ..... 51 Chapter 6: Pin configuration LPC2101/2102/2103 pinout ....60 Pin description for LPC2101/02/03 ..61 Chapter 7: Pin connect block Features .

  • Page 274: User Manual

    Auto-baud......114 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 275: User Manual

    State: 0x60......153 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual...

  • Page 276: User Manual

    Register description ....181 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 277: User Manual

    0xE007 4028)......207 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...

  • Page 278: User Manual

    ISP data format..... . . 231 19.7 Code Read Protection (CRP) ... . 235 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved. User manual Rev. 01 — 12 January 2006...
  • Page 279 Trademarks......266 © Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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