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Philips Semiconductors
INTERRUPTS
3. INTERRUPTS
The P89LPC920/921/922 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the
P89LPC920/921/922's 12 interrupt sources.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or
IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority
registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other
interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which
request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of
the same priority level.
Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether
each interrupt may wake up the CPU from a Power down mode.
Interrupt priority structure
There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH
(x = 0,1) and can therefore be assigned to one of four levels, as shown in Table .
Table 3-1: Interrupt priority level
Priority bits
IPxH
0
0
1
1
2003 Dec 8
IPx
0
1
0
1
25
User's Manual - Preliminary -
P89LPC920/921/922
Interrupt priority level
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
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