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Philips Semiconductors
Volume 1
Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 75
register, these additional registers allow easier and faster access to the physical port pins.
Table 75:
Fast GPIO port 0 Mask byte and half-word accessible register description
Register
Register
name
length (bits)
& access
FIO0MASK0 8 (byte)
FIO0MASK1 8 (byte)
FIO0MASK2 8 (byte)
FIO0MASK3 8 (byte)
FIO0MASKL 16
(half-word)
FIO0MASKU 16
(half-word)
Table 76:
Fast GPIO port 1 Mask byte and half-word accessible register description
Register
Register
name
length (bits)
& access
FIO1MASK0 8 (byte)
FIO1MASK1 8 (byte)
FIO1MASK2 8 (byte)
FIO1MASK3 8 (byte)
FIO1MASKL 16
(half-word)
FIO1MASKU 16
(half-word)
8.4.3 GPIO port Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000 and
Port 1: IO1PIN - 0xE002 8010; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014
and Port 1: FIO1PIN - 0x3FFF C034)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the IOPIN register.
User manual
and
Table
76, too. Next to providing the same functions as the FIOMASK
Address
Description
0x3FFF C010
Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register
corresponds to P0.0 ... bit 7 to P0.7.
0x3FFF C011
Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register
corresponds to P0.8 ... bit 7 to P0.15.
0x3FFF C012
Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register
corresponds to P0.16 ... bit 7 to P0.23.
0x3FFF C013
Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C001
Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in
FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C012
Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in
FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.
Address
Description
0x3FFF C010
Fast GPIO Port 1 Mask register 0. Bit 0 in FIO1MASK0 register
corresponds to P1.0 ... bit 7 to P1.7.
0x3FFF C011
Fast GPIO Port 1 Mask register 1. Bit 0 in FIO1MASK1 register
corresponds to P1.8 ... bit 7 to P1.15.
0x3FFF C012
Fast GPIO Port 1 Mask register 2. Bit 0 in FIO1MASK2 register
corresponds to P1.16 ... bit 7 to P1.23.
0x3FFF C013
Fast GPIO Port 1 Mask register 3. Bit 0 in FIO1MASK3 register
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C001
Fast GPIO Port 1 Mask Lower half-word register. Bit 0 in
FIO1MASKL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C012
Fast GPIO Port 1 Mask Upper half-word register. Bit 0 in
FIO1MASKU register corresponds to P1.16 ... bit 15 to P1.31.
Rev. 01 — 15 August 2005
UM10139
Chapter 8: GPIO
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
86
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