Usb End Of Transfer Interrupt Status Register (Usbeotintst - 0Xe009 00A0); Usb End Of Transfer Interrupt Clear Register (Usbeotintclr - 0Xe009 00A4) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 215: USB DMA Interrupt Enable register (USBDMAIntEn - address 0xE009 0094) bit
Bit
0
1
2
31:3 -
14.8.20 USB End of Transfer Interrupt Status register (USBEoTIntSt -
0xE009 00A0)
When the transfer completes for the descriptor, either normally (descriptor is retired) or
because of an error, this interrupt occurs. The cause of the interrupt generation will be
recorded in the DD_Status field of the descriptor. The USBEoTIntSt is a read only register.
Table 216: USB End of Transfer Interrupt Status register (USBEoTIntSt - address
Bit
31:0
14.8.21 USB End of Transfer Interrupt Clear register (USBEoTIntClr -
0xE009 00A4)
Writing 1 into the register will clear the corresponding interrupt from the End of Transfer
Interrupt Status register. Writing 0 will not have any effect. The USBEoTIntClr is a write
only register.
Table 217: USB End of Transfer Interrupt Clear register (USBEoTIntClr - address
Bit
31:0 EPxx
9397 750 XXXXX
User manual
description
Symbol
End_of_Transfer_Interrupt_En
New_DD_Request_Interrupt_En
System_Error_Interrupt_En
0xE009 00A0s) bit description
Symbol Value Description
EPxx Endpoint xx (0
0 There is no End of Transfer interrupt request for endpoint xx.
1 There is an End of Transfer Interrupt request for endpoint xx.
0xE009 00A4) bit description
Symbol Value Description
Clear endpoint xx (0
0 Ne effect.
1 Clear the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
Value Description
End of Transfer Interrupt enable bit.
0 The End of Transfer Interrupt is disabled.
1 The End of Transfer Interrupt is enabled.
New DD Request Interrupt enable bit.
0 The New DD Request Interrupt is
disabled.
1 The New DD Request Interrupt is
enabled.
System Error Interrupt enable bit.
0 The System Error Interrupt is disabled.
1 The System Error Interrupt is enabled.
- Reserved, user software should not write
ones to reserved bits. The value read from
a reserved bit is not defined.
≤ ≤
xx 31) End of Transfer Interrupt request.
≤ ≤
xx 31) End of Transfer Interrupt request. 0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Reset
value
0
0
0
NA
Reset
value
0
Reset
value
219