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Philips Semiconductors
Volume 1
1.3 Applications
1.4 Device information
Table 1:
LPC2141/2/4/6/8 device information
Device
Number
On-chip
of pins
SRAM
LPC2141
64
8 kB
LPC2142
64
16 kB
LPC2144
64
16 kB
LPC2146
64
32 kB + 8 kB
LPC2148
64
32 kB + 8 kB
[1]
1.5 Architectural overview
The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced
High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI
User manual
•
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 µs.
•
On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30 MHz and with an external oscillator up to 50 MHz.
•
Power saving modes include Idle and Power-down.
•
Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
•
Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).
•
Single power supply chip with Power-On Reset (POR) and BOD circuits:
– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads.
•
Industrial control
•
Medical systems
•
Access control
•
Point-of-sale
•
Communication gateway
•
Embedded soft modem
•
General purpose applications
Endpoint
USB RAM
2 kB
2 kB
2 kB
[1]
2 kB
[1]
2 kB
While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time
by the CPU as a general purpose RAM for data and code storage.
Rev. 01 — 15 August 2005
Chapter 1: Introductory information
On-chip
Number of
FLASH
10-bit ADC
channels
32 kB
6
64 kB
6
128 kB
14
256 kB
14
512 kB
14
UM10139
Number of
Note
10-bit DAC
channels
-
-
1
-
1
UART1 with full modem
interface
1
UART1 with full modem
interface
1
UART1 with full modem
interface
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
4
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