Example Timer Operation - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 244: External match control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
00
01
10
11

15.6 Example timer operation

Figure 56
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 57
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
PCLK
Prescale
counter
Timer
counter
Timer counter
reset
Iterrupt
Fig 56. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
Prescale
counter
Timer
counter
TCR[0]
(counter enable)
Iterrupt
Fig 57. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
User manual
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
2 0 1 2
4 5
2 0 1 2
4 5
1
Rev. 01 — 15 August 2005
0 1 2 0
6
0
6
0
UM10139
Chapter 15: TIMER0 and TIMER1
1 2 0 1
0 1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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