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Philips Semiconductors
Volume 1
11.7.5 I
I2C1, I2C1ADR - address 0xE005 C00C)
These registers are readable and writable, and is only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the general
call bit. When this bit is set, the general call address (0x00) is recognized.
Table 140: I
Bit Symbol
0
7:1 Address
11.7.6 I
0xE001 C010 and I2C1, I2C1SCLH - 0xE0015 C010)
Table 141: I
Bit
15:0
11.7.7 I
0xE001 C014; I2C1 - I2C1SCLL: 0xE0015 C014)
Table 142: I
Bit
15:0
11.7.8 Selecting the appropriate I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK cycles for the SCL high
time, I2SCLL defines the number of PCLK cycles for the SCL low time. The frequency is
determined by the following formula (PCLK is the frequency of the peripheral bus VPB):
The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a 400 kHz I
rate. The value of the register must ensure that the data rate is in the I
of 0 through 400 kHz. Each register value must be greater than or equal to 4.
gives some examples of I
I2SCLH values.
User manual
2
C Slave Address register (I2ADR: I2C0, I2C0ADR - 0xE001 C00C and
2
C Slave Address register (I2ADR: I2C0, I2C0ADR - address 0xE001 C00C and
I2C1, I2C1ADR - address 0xE005 C00C) bit description
Description
GC
General Call enable bit.
2
The I
C device address for slave mode.
2
C SCL High duty cycle register (I2SCLH: I2C0, I2C0SCLH -
2
C SCL High Duty Cycle register (I2SCLH: I2C0, I2C0SCLH - address
0xE001 C010 and I2C1, I2C1SCLH - address 0xE005 C010) bit description
Symbol
Description
SCLH
Count for SCL HIGH time period selection.
2
C SCL Low duty cycle register (I2SCLL: I2C0 - I2C0SCLL:
2
C SCL Low Duty Cycle register (I2SCLL: I2C0, I2C0SCLL - address 0xE001 C014
and I2C1, I2C1SCLL - address 0xE005 C014) bit description
Symbol
Description
SCLL
Count for SCL LOW time period selection.
Rev. 01 — 15 August 2005
2
C data rate and duty cycle
I 2 C
=
-------------------------------------------------------- -
bitfrequency
I2CSCLH
2
C-bus rates based on PCLK frequency and I2SCLL and
UM10139
Chapter 11: I
2
C interface is set to
PCLK
+
I2CSCLL
2
C data rate range
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C interfaces
Reset value
0
0x00
Reset value
0x0004
Reset value
0x0004
(7)
2
C-bus
2
C
Table 143
146
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