Pll Control Register (Pll0Con - 0Xe01F C080, Pll1Con - 0Xe01F C0A0) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
PLLC
0
PSEL[1:0]
PLLE
0
F
OSC
PLOCK
MSEL[4:0]
Fig 9. PLL block diagram
3.8.2 PLL Control register (PLL0CON - 0xE01F C080, PLL1CON -
0xE01F C0A0)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see
0xE01F C08C, PLL1FEED - 0xE01F C0AC)"
register (PLL0CFG - 0xE01F C084, PLL1CFG - 0xE01F C0A4)" on page
User manual
Direct
PD
Bypass
PHASE-
FREQUENCY
DETECTOR
PD
CD
F
OUT
DIV-BY-M
MSEL<4:0>
Rev. 01 — 15 August 2005
CLOCK
SYNCHRONIZATION
PD
1
F
CCO
0
CCO
Section 3.8.7 "PLL Feed register (PLL0FEED -
and Section 3.8.3 "PLL Configuration
UM10139
Chapter 3: System Control Block
CD
0
/2P
0
1
1
30).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
CCLK
29