Table of Contents
Advertisement
Philips Semiconductors
Volume 1
3.9.4 Power control usage notes
After every reset, the PCONP register contains the value that enables all interfaces and
peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user's application has no need to
access the PCONP in order to start using any of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
3.10 Reset
Reset has two sources on the LPC2141/2/4/6/8: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the Wakeup Timer (see description in
"Wakeup timer"
is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip circuitry has completed its initialization. The relationship between Reset, the
oscillator, and the Wakeup Timer are shown in
The Reset glitch filter allows the processor to ignore external reset pulses that are very
short, and also determines the minimum duration of RESET that must be asserted in
order to guarantee a chip reset. Once asserted, RESET pin can be deasserted only when
crystal oscillator is fully running and an adequate signal is present on the X1 pin of the
microcontroller. Assuming that an external crystal is used in the crystal oscillator
subsystem, after power on, the RESET pin should be asserted for 10 ms. For all
subsequent resets when crystal oscillator is already running and stable signal is on the X1
pin, the RESET pin needs to be asserted for 300 ns only.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
External and internal Resets have some small differences. An external Reset causes the
value of certain pins to be latched to configure the part. External circuitry cannot
determine when an internal Reset occurs in order to allow setting up those special pins,
so those latches are not reloaded during an internal Reset. Pins that are examined during
an external Reset for various purposes are: P1.20/TRACESYNC, P1.26/RTCK (see
chapters "Pin Configuration" on page 66 and "Pin Connect Block" on page 75). Pin P0.14
(see "Flash Memory System and Programming" chapter on page 291) is examined by
on-chip bootloader when this code is executed after every Reset.
It is possible for a chip Reset to occur during a Flash programming or erase operation.
The Flash memory will interrupt the ongoing operation and hold off the completion of
Reset to the CPU until internal Flash high voltages have settled.
User manual
in this chapter), causing reset to remain asserted until the external Reset
Rev. 01 — 15 August 2005
UM10139
Chapter 3: System Control Block
Section 3.12
Figure
10.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
38
Advertisement
Table of Contents
