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Philips Semiconductors
Volume 1
Table 16:
Bit
0
1
7:2
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
3.8.3 PLL Configuration register (PLL0CFG - 0xE01F C084, PLL1CFG -
0xE01F C0A4)
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 3.8.7 "PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED -
0xE01F C0AC)" on page
divider values are found in the PLL Frequency Calculation section on page 33.
Table 17:
Bit
4:0
6:5
7
User manual
PLL Control register (PLL0CON - address 0xE01F C080, PLL1CON - address
0xE01F C0A0) bit description
Symbol
Description
PLLE
PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register,
PLLC
PLL Connect. When PLLC and PLLE are both set to one, and after a
valid PLL feed, connects the PLL as the clock source for the
microcontroller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register,
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
32). Calculations for the PLL frequency, and multiplier and
PLL Configuration register (PLL0CFG - address 0xE01F C084, PLL1CFG - address
0xE01F C0A4) bit description
Symbol
Description
MSEL
PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations.
Note: For details on selecting the right value for MSEL see
3.8.9 "PLL frequency calculation" on page
PSEL
PLL Divider value. Supplies the value "P" in the PLL frequency
calculations.
Note: For details on selecting the right value for PSEL see
3.8.9 "PLL frequency calculation" on page
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 15 August 2005
Chapter 3: System Control Block
Table
18.
Table
33.
33.
UM10139
Reset
value
0
0
18.
NA
Reset
value
0
Section
0
Section
NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
30
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