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Philips Semiconductors
Volume 1
If the software makes the Read Enable bit low midway, the reading will be terminated. In
this case the data will remain in the EP_RAM. When the Read Enable signal is made high
again for this endpoint, data will be read from the beginning.
For writing data to an endpoint buffer, Write Enable bit (WR_EN in
made high and software should write to the Transmit Packet Length register
(Section
continuously in the Transmit Data register.
When the control logic receives the number of bytes programmed in the Transmit Packet
Length register, it will reset the Write Enable bit. The TxENDPKT bit is set in the Device
Interrupt Status register. The software should issue a Validate Buffer (refer to
14.9.14 "Validate Buffer (Command: 0xFA, Data: none)" on page
endpoint is now ready to send the packet. If the software resets this bit midway, writing will
start again from the beginning.
A synchronization mechanism is used to transfer data between the two clock domains i.e.
AHB slave clock and the USB bit clock at 12 MHz. This synchronization process takes up
to 5 clock cycles of the slow clock (i.e. 12 MHz) for reading/writing from/to a register
before the next read/write can happen. The AHB HREADY output from the USB device is
driven appropriately to take care of the timing.
Both Read Enable and Write Enable bits can be high at the same time for the same logical
endpoint. The interleaved read and write operation is possible.
14.8.9 USB Command Code register (USBCmdCode - 0xE009 0010)
This register is used for writing the commands. The commands written here will get
propagated to the Protocol Engine and will be executed there. After executing the
command, the register will be empty, and the "CCEMTY" bit of the Interrupt Status register
is set high. See
details. The USBCmdCode is a write only register.
Table 204: USB Command Code register (USBCmdCode - address 0xE009 0010) bit
Bit
7:0
15:8
23:16 CMD_CODE
31:24 -
14.8.10 USB Command Data register (USBCmdData - 0xE009 0014)
This is a read-only register which will carry the data retrieved after executing a command.
When this register is ready, the "CD_FULL" bit of the Device Interrupt Status register is
set. The CPU can poll this bit or enable an interrupt corresponding to this to sense the
arrival of the data.The data is always one-byte wide. See
command description" on page 222
9397 750 XXXXX
User manual
14.8.6) the number of bytes it is going to send in the packet. It can then write data
Section 14.9 "Protocol engine command description" on page 222
description
Symbol
Description
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
CMD_PHASE
The command phase.
The code for the command.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
Section 14.9 "Protocol engine
for details.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Table
203) should be
Section
230) command. The
for
Reset value
NA
0x00
0x00
NA
213
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