Page 1 INTEGRATED CIRCUITS LPC2119/2129 LPC2292/2294 User Manual Preliminary Release January 08, 2004 PHILIPS Philips Semiconductors...
Page 2 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 January 08, 2004...
Page 3 LPC2119/2129/2292/2294 Registers ..........21 LPC2119/2129/2292/2294 Memory Addressing ....... . 32 Memory Maps .
Page 4 Pin Description for LPC2119/2129 ........
Page 5 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CAN Controllers and Acceptance Filter ........158 Features .
Page 6 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Flash Memory System and Programming ........228 Flash Memory System .
Page 7 LPC2119/2129/2292/2294 Block Diagram ........
Page 8 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 January 08, 2004...
Page 9: List Of Tables
Table 4: LPC2119/2129/2292/2294 Memory Mapping Modes........36 Table 5: Address Ranges of External Memory Banks (LPC2292/2294only) .
Page 10 Table 57: Pin Connect Block Register Map ..........100 Table 58: Pin Function Select Register 0 for LPC2119/2129 (PINSEL0 - 0xE002C000) ... . . 101 Table 59: Pin Function Select Register 0 for LPC2292/2294 (PINSEL0 - 0xE002C000) .
Page 11 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 113: SPI Pin Description ............152 Table 114: SPI Register Map .
Page 12 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 166: PWM Timer Control Register (PWMTCR - 0xE0014004) ......199 Table 167: PWM Match Control Register (PWMMCR - 0xE0014014) .
Page 13 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 223: ETM Configuration ............254 Table 224: ETM Pin Description .
Page 14: Document Revision History
ARM-based Microcontroller LPC2119/2129/2292/2294 DOCUMENT REVISION HISTORY 2003 Dec 03: • Prototype LPC2119/2129/2292/2294 User Manual created from the design specification. 2003 Dec 09: • External Memory Controller and Pin Connect Block chapters updated. 2003 Dec 15/16: • System Control Block chapter updated.
Page 15 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 January 08, 2004...
Page 16: Introduction
LPC2119/2129/2292/2294 1. INTRODUCTION GENERAL DESCRIPTION The LPC2119/2129/2292/2294 are based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty.
Page 17: Applications
On-chip FLASH Note channels LPC2119 16 kB 128 kB LPC2129 16 kB 256 kB with external LPC2292 16 kB 256 kB memory interface with external LPC2294 16 kB 256 kB memory interface Table 1: LPC2119/2129/2292/2294 device information Introduction January 08, 2004...
Page 18: Architectural Overview
LPC2119/2129/2292/2294 ARCHITECTURAL OVERVIEW The LPC2119/2129/2292/2294 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions.
Page 19: On-Chip Static Ram
LPC2119/2129/2292/2294 ON-CHIP STATIC RAM The LPC2119/2129/2292/2294 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses. The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM.
Page 20: Block Diagram
P3.31:0 Watchdog PWM6:1 PWM0 Timer Real Time System Clock Control * Shared with GPIO When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available LPC2292/2294 only. LPC2294 only. Figure 1: LPC2119/2129/2292/2294 Block Diagram Introduction January 08, 2004...
Page 21: Lpc2119/2129/2292/2294 Registers
RTC is enabled. Registers in LPC2119/2129/2292/2294 are 8, 16 or 32 bits wide. For 8 bit registers shown in Table 2, bit residing in the MSB (The Most Significant Bit) column corresponds to the bit 7 of that register, while bit in the LSB (The Least Significant Bit) column corresponds to the bit 0 of the same register.
Page 22 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value Watchdog 0xE000000C WDTV timer value 32 bit data 0xFF register TIMER0 T0 Interrupt 0xE0004000 T0IR Register Int. Int. Int. Int. Int.
Page 23 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value External Match 6 reserved (-) bits T0 External Control 2 0xE000403C T0EMR Match External Match External Match Ext. Ext. Ext. Register...
Page 24 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value T1 Capture 0xE0008038 T1CR3 32 bit data Register 3 External Match External Match 4 reserved (-) bits T1 External Control 3...
Page 25 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value U1 Receiver U1RBR Buffer 8 bit data defined (DLAB=0) Register U1 Transmit 0xE0010000 U1THR Holding 8 bit data (DLAB=0) Register U1 Divisor...
Page 26 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value 0xE001400C Prescale 32 bit data Register 0xE0014010 Prescale 32 bit data Counter Stop Reset Stop Reset Int. on 11 reserved (-) bits...
Page 27 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value C Slave 0xE001C00C Address 7 bit data Register SCL Duty Cycle 0xE001C010 16 bit data 0x04 SCLH Register High Half Word...
Page 28 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value Interrupt 0xE0024000 Location Register Clock Tick 0xE0024004 15 bit data Counter Clock Control 0xE0024008 CTTEST Register Counter Increment 0xE002400C CIIR Interrupt...
Page 29 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value Alarm value 0xE0024060 6 bit data for Seconds Alarm value 0xE0024064 6 bit data for Minutes Alarm value 0xE0024068 5 bit data...
Page 30 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value Pin function 0xE002C000 select 32 bit data SEL0 register 0 Pin function 0xE002C004 select 32 bit data SEL1 register 1 EDGE...
Page 31 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 2: LPC2119/2129/2292/2294 Registers Address Reset Name Description Access Offset Value reserved (-) 22 bits Power control 0xE01FC0C4 PCONP 0x3BE peripherals PWM0 URT1 URT0 TIM1 TIM0 VPB divider 0xE01FC100 2 bit data...
Page 32: Lpc2119/2129/2292/2294 Memory Addressing
2. LPC2119/2129/2292/2294 MEMORY ADDRESSING MEMORY MAPS The LPC2119/2129/2292/2294 incorporates several distinct memory regions, shown in the following figures. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address re-mapping, which is described later in this section.
Page 33: Figure 3: Peripheral Memory Map
An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately. LPC2119/2129/2292/2294 Memory Addressing January 08, 2004...
Page 34: Figure 4: Ahb Peripheral Map
0xFFFF 4000 (AHB peripheral #124) 0xFFFF 0000 0xFFE1 0000 (AHB peripheral #3) 0xFFE0 C000 (AHB peripheral #2) 0xFFE0 8000 (AHB peripheral #1) 0xFFE0 4000 (AHB peripheral #0) 0xFFE0 0000 Figure 4: AHB Peripheral Map LPC2119/2129/2292/2294 Memory Addressing January 08, 2004...
Page 35: Figure 5: Vpb Peripheral Map
(VPB peripheral #4) 0xE001 0000 UART0 (VPB peripheral #3) 0xE000 C000 TIMER1 (VPB peripheral #2) 0xE000 8000 TIMER0 (VPB peripheral #1) 0xE000 4000 Watchdog Timer (VPB peripheral #0) 0xE000 0000 Figure 5: VPB Peripheral Map LPC2119/2129/2292/2294 Memory Addressing January 08, 2004...
Page 36: Lpc2119/2129/2292/2294 Memory Re-Mapping And Boot Block
Memory Map Concepts and Operating Modes The basic concept on the LPC2119/2129/2292/2294 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.
Page 37 Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Details on re-mapping and examples can be found in System Control Block on page 48. LPC2119/2129/2292/2294 Memory Addressing January 08, 2004...
Page 38: Figure 6: Map Of Lower Memory Is Showing Re-Mapped And Re-Mappable Areas (128 Kb Flash)
Active interrupt vectors (from Flash, SRAM, or Boot Block) 0x0000 0000 Note: memory regions are not drawn to scale. Figure 6: Map of lower memory is showing re-mapped and re-mappable areas (128 kB Flash). LPC2119/2129/2292/2294 Memory Addressing January 08, 2004...
Page 39: Prefetch Abort And Data Abort Exceptions
The regions are: • Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2119/2129/2292/2294, this is: - Address space between On-Chip Non-Volatile Memory and On-Chip SRAM, labelled "Reserved for On-Chip Memory" in Figure 2 and Figure 6.
Page 40: External Memory Controller (Emc)
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 3. EXTERNAL MEMORY CONTROLLER (EMC) This module is available in LPC2292 and LPC2294 only. FEATURES • Supports static memory-mapped devices including RAM, ROM, flash, burst ROM, and some external I/O devices. • Asynchronous page mode read operation in non-clocked memory subsystems •...
Page 41: Pin Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PIN DESCRIPTION Pin Name Type Pin Description Input/ D[31:0] External memory data lines. Output A[23:0] Output External memory address lines. Output Low-active Output Enable signal. BLS[3:0] Output Low-active Byte Lane Select signals.
Page 42 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Bank Configuration Registers 0 - 3 (BCFG0-3 - 0xFFE00000-0C) BCFG0-3 Name Function Reset Value This field controls the minimum number of “idle” CCLK cycles that the EMC maintains between read and write accesses in this bank, and between an access in another bank...
Page 43: External Memory Interface
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 EXTERNAL MEMORY INTERFACE External memory interface depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register). Furthermore, choice of the memory chip(s) will require an adequate setup of RBLE bit in BCFG register, too. RBLE = 0 in case of 8-bit based external memories, while memory chips capable of accepting 16 or 32 bit wide data will work with RBLE = 1.
Page 44: Figure 8: 16 Bit Bank External Memory Interfaces
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 BLS[1] BLS[0] BLS[1] BLS[0] D[15:0] IO[15:0] D[15:8] IO[7:0] D[7:0] IO[7:0] A[a_m:0] A[a_m:0] A[a_m:0] A[a_b:1] A[a_b:1] a) 16 bit wide memory bank interfaced a) 16 bit wide memory bank interfaced to 8 bit memory chips...
Page 45: Typical Bus Sequences
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 TYPICAL BUS SEQUENCES Following figures show typical external read and write access cycles. XCLK is the clock signal avalable on P3.23. While not necessary used by external memory, In these examples it is used to provide time reference (XCLK and PCLK were set to have the same frequency).
Page 46: External Memory Selection
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 EXTERNAL MEMORY SELECTION Based on the description of the EMC operation and external memory in general (appropriate read and write access times t respecitely), the following table can be constructed and used for external memory selection. t...
Page 47 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 External Memory Controller (EMC) January 08, 2004...
Page 48: System Control Block
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 4. SYSTEM CONTROL BLOCK SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: •...
Page 49: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 12: Summary of System Control Registers Reset Address...
Page 50: Crystal Oscillator
PLL is running and connected. Refer to the PLL description in this chapter for details. Onboard oscillator in LPC2119/2129/2292/2294 can operate in one of two modes: slave mode and oscillation mode. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Cc in Figure 12, drawing a), with an amplitude of at least 200 mVrms.
Page 51: External Interrupt Inputs
ARM-based Microcontroller LPC2119/2129/2292/2294 EXTERNAL INTERRUPT INPUTS The LPC2119/2129/2292/2294 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from the Power Down mode. Register Description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the LPC2119/2129/2292/2294 from Power Down mode.
Page 52 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 15: External Interrupt Flag Register (EXTINT - 0xE01FC140) Reset EXTINT Function Description Value In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin.
Page 53 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) Reset EXTWAKE Function Description Value EXTWAKE3 When one, assertion of EINT3 will wake up the processor from Power Down mode. Reserved, user software should not write ones to reserved bits. The value read Reserved from a reserved bit is not defined.
Page 54 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 18: External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C) Reset EXTPOLAR Function Description Value When 0, EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). EXTPOLAR0 When 1, EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).
Page 55: Figure 13: External Interrupt Logic
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Wakeup Enable VPB Read (one bit of EXTWAKE) of EXTWAKE EINTi to VPB Bus Data Wakeup Timer (Figure 15) Glitch EINTi Filter pclk Interrupt Flag (one bit of EXTINT) EXTPOLARi to VIC...
Page 56: Memory Mapping Control
*: The hardware reset value of the MAP bits is 00 for LPC2119/2129/2292/2294 parts. The apparent reset value that the user will see will be altered by the Boot Loader code, which always runs initially at reset. User documentation will reflect this difference.
Page 57: Pll (Phase Locked Loop)
10 MHz to 60 MHz using a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2119/2129/2292/2294 due to the upper frequency limit of the CPU).
Page 58: Figure 14: Pll Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Clock PLLC PLLE Synchronization Direct PSEL[1:0] Bypass Phase- Frequency PLOCK Detector cclk fout Div-by-M msel<4:0> MSEL[4:0] Figure 14: PLL Block Diagram PLL Control Register (PLLCON - 0xE01FC080) The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Page 59 See PLLSTAT register, Table 24. PLL Connect. When PLLC and PLLE are both set to one, and after a valid PLL feed, connects the PLL as the clock source for the LPC2119/2129/2292/2294. Otherwise, PLLC the oscillator clock is used directly by the LPC2119/2129/2292/2294.
Page 60 Read-back for the PLL Connect bit. When PLLC and PLLE are both one, the PLL is connected as the clock source for the LPC2119/2129/2292/2294. When either PLLC PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the LPC2119/2129/2292/2294.
Page 61 10 MHz to 25 MHz. • cclk is in the range of 10 MHz to F (the maximum allowed frequency for the LPC2119/2129/2292/2294). • F is in the range of 156 MHz to 320 MHz.
Page 62 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Procedure for Determining PLL Settings If a particular application uses the PLL, its configuration may be determined as follows: 1. Choose the desired processor operating frequency (cclk). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc.
Page 63: Power Control
LPC2119/2129/2292/2294 POWER CONTROL The LPC2119/2129/2292/2294 supports two reduced power modes: Idle mode and Power Down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
Page 64 The bit numbers correspond to the related peripheral number as shown in the VPB peripheral map in the LPC2119/2129/2292/2294 Memory Addressing section. Table 31: Power Control for Peripherals Register for LPC2119/2129 (PCONP - 0xE01FC0C4) Reset...
Page 65 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 32: Power Control for Peripherals Register for LPC2292/2294 (PCONP - 0xE01FC0C4) Reset PCONP Function Description Value PCURT1 When 1, UART1 is enabled. When 0, UART1 is disabled to conserve power. PCPWM0 When 1, PWM0 is enabled. When 0, PWM0 is disabled to conserve power.
Page 66: Reset
RESET Reset has two sources on the LPC2119/2129/2292/2294: the RESET pin and Watchdog Reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see Wakeup Timer description later in this chapter), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the Flash controller has completed its initialization.
Page 67: Vpb Divider
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 VPB DIVIDER The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). The VPB Divider serves two purposes. The first is to provides peripherals with desired pclk via VPB bus so that they can operate at the speed chosen for the ARM processor.
Page 68: Figure 16: Vpb Divider Connections
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Crystal Oscillator Processor Clock External Clock Source (cclk) VPB Divider VPB Clock (pclk) Figure 16: VPB Divider Connections System Control Block January 08, 2004...
Page 69: Wakeup Timer
OR the signals to wake the device. The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2119/2129/2292/229 from capturing the bus or line activity that wakes it up.
Page 70: Memory Accelerator Module (Mam)
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 5. MEMORY ACCELERATOR MODULE (MAM) INTRODUCTION Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls. The method used is to split the Flash memory into two banks, each capable of independent accesses.
Page 71: Figure 17: Simplified Block Diagram Of The Memory Accelerator Module
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Flash programming operations are not controlled by the Memory Accelerator Module, but are handled as a separate function. A “boot block” sector contains Flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow serial programming of the Flash memory.
Page 72: Memory Accelerator Module Operating Modes
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 In order to preclude the possibility of stale data being read from the Flash memory, the MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation. Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed.
Page 73: Mam Configuration
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 MAM CONFIGURATION After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.
Page 74: Mam Usage Notes
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 MAM Control Register (MAMCR - 0xE01FC000) Two configuration bits select the three MAM operating modes, as shown in Table 38. Following Reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required.
Page 75 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Memory Accelerator Module (MAM) January 08, 2004...
Page 76: Vectored Interrupt Controller (Vic)
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 6. VECTORED INTERRUPT CONTROLLER (VIC) FEATURES • ARM PrimeCell™ Vectored Interrupt Controller • 32 interrupt request inputs • 16 vectored IRQ interrupts • 16 priority levels dynamically assigned to interrupt requests • Software interrupt generation...
Page 77: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The VIC implements the registers shown in Table 40. More detailed descriptions follow. Table 40: VIC Register Map Reset Address Name Description Access Value* IRQ Status Register. This register reads out the state of those interrupt...
Page 78 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 40: VIC Register Map Reset Address Name Description Access Value* 0xFFFF F128 VICVectAddr10 Vector address 10 register 0xFFFF F12C VICVectAddr11 Vector address 11 register 0xFFFF F130 VICVectAddr12 Vector address 12 register...
Page 79: Vic Registers
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 VIC REGISTERS This section describes the VIC registers in the order in which they are used in the VIC logic, from those closest to the interrupt request inputs to those most abstracted for use by software. For most people, this is also the best order to read about the registers when learning the VIC.
Page 80 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Interrupt Enable Register (VICIntEnable - 0xFFFFF010, Read/Write) This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ. Table 44: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write)
Page 81 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 FIQ Status Register (VICFIQStatus - 0xFFFFF004, Read Only) This register reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.
Page 82 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write) When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read. Table 52: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write)
Page 83: Interrupt Sources
External Interrupt 2 (EINT2) System Control External Interrupt 2 (EINT2) A/D Converter CAN and Acceptance Filter 1 ORed CAN, LUTerr int 2x(Tx int, Rx int) LPC2119/2129/2292/2294 20-23 2x(Tx int, Rx int) LPC2294 only 24-27 Vectored Interrupt Controller (VIC) January 08, 2004...
Page 84: Figure 18: Block Diagram Of The Vectored Interrupt Controller
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 nVICFIQIN Interrupt Request, Masking, and Selection Non-vectored FIQ Interrupt Logic SoftIntClear IntEnableClear [31:0] [31:0] nVICFIQ FIQStatus [31:0] SoftInt IntEnable FIQStatus [31:0] [31:0] [31:0] VICINT IRQStatus SOURCE Non-vectored IRQ Interrupt Logic [31:0] [31:0]...
Page 85: Vic Usage Notes
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 VIC USAGE NOTES If user’s code is runing from the on-chip RAM and an aplication uses interrupts, interrupt vectors must be re-mapped to flash address 0x0. This is necessary because all the exception vectors are located at addresses 0x0 and above. This is easily achieved by configuring MEMMAP register (located in System Control Block) to User RAM mode.
Page 86: Pin Configuration
LPC2119/2129 PINOUT P1.20/TRACESYNC P0.21/PWM5/CAP1.3 P0.17/CAP1.2 /SCK1/MAT1.2 P0.22/CAP0.0/MAT0.0 P0.16/EINT0/MAT0.2/CAP0.2 P0.23/RD2 P0.15/RI1/EINT2 P1.19/TRACEPKT3 P1.21/PIPESTAT0 P0.24/TD2 P0.14/DCD1/EINT1 P1.18/TRACEPKT2 P1.22/PIPESTAT1 P0.25/RD1 P0.13/DTR1/MAT1.1 P0.12/DSR1/MAT1.0 P0.27/AIN0/CAP0.1/MAT0.1 P0.11/CTS1/CAP1.1 P1.17/TRACEPKT1 P1.23/PIPESTAT2 P0.28/AIN1/CAP0.2/MAT0.2 P0.10/RTS1/CAP1.0 P0.29/AIN2/CAP0.3/MAT0.3 P0.9/RxD1/PWM6/EINT3 P0.30/AIN3/EINT3/CAP0.0 P0.8/TxD1/PWM4 P1.16/TRACEPKT0 Figure 19: LPC2119/2129 64-pin package Pin Configuration January 08, 2004...
Page 87: Pin Description For Lpc2119/2129
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PIN DESCRIPTION FOR LPC2119/2129 Pin description for LPC2119/2129 and a brief of corresponding functions are shown in the following table. Table 55: Pin description for LPC2119/2129 LQFP64 Type Description Name Pin # P0.0...
Page 88 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 55: Pin description for LPC2119/2129 LQFP64 Type Description Name Pin # P0.12 DSR1 Data Set Ready input for UART1. MAT1.0 Match output for TIMER1, channel 0. P0.13 DTR1 Data Terminal Ready output for UART1.
Page 89 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 55: Pin description for LPC2119/2129 LQFP64 Type Description Name Pin # P0.28 AIN1 A/D converter, input 1. This analog input is always connected to its pin. CAP0.2 Capture input for TIMER0, channel 2.
Page 90 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 55: Pin description for LPC2119/2129 LQFP64 Type Description Name Pin # P1.29 Test Clock for JTAG interface. P1.30 Test Mode Select for JTAG interface. P1.31 TRST Test Reset for JTAG interface.
Page 91: Lpc2292/2294 Pinout
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 LPC2292/2294 PINOUT P2.3/D3 P2.22/D22 P2.2/D2 P2.1/D1 P0.21/PWM5/RD3 /CAP1.3 P0.22/TD3 /CAP0.0/MAT0.0 P0.23/RD2 P1.20/TRACESYNC P1.19/TRACEPKT3 P0.17/CAP1.2/SCK1/MAT1.2 P0.24/TD2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2 P2.23/D23 P2.0/D0 P2.24/D24 P3.30/BLS1 P2.25/D25 P3.31/BLS0 P2.26/D26/BOOT0 P1.21/PIPESTAT0 P1.18/TRACEPKT2 P2.27/D27/BOOT1 P0.14/DCD1/EINT1 P2.28/D28 P1.0/CS0 P2.29/D29 P1.1/OE P2.30/D30/AIN4...
Page 92: Pin Description For Lpc2292/2294
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PIN DESCRIPTION FOR LPC2292/2294 Pin description for LPC2292/2294 and a brief of corresponding functions are shown in the following table.Pin Description Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin #...
Page 93 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P0.10 RTS1 Request to Send output for UART1. CAP1.0 Capture input for TIMER1, channel 0. P0.11 CTS1 Clear to Send input for UART1.
Page 94 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P0.22 CAN3 transmitter output (available in LPC2294 only). CAP0.0 Capture input for TIMER0, channel 0. MAT0.0 Match output for TIMER0, channel 0.
Page 95 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P1.20 TRACESYNCTrace Synchronization. Standard I/O port with internal pull-up. LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as a Trace port after reset.
Page 96 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P2.5 External memory data line 5. P2.6 External memory data line 6. P2.7 External memory data line 7. P2.8 External memory data line 8.
Page 97 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P2.26 External memory data line 26. BOOT0 While RESET is low, together with BOOT1 controls booting and internal operation. Internal pullup ensures high state if pin is left unconnected.
Page 98 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P3.7 External memory address line 7. P3.8 External memory address line 8. P3.9 External memory address line 9. P3.10 External memory address line 10.
Page 99 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 56: Pin description for LPC2292/2294 LQFP144 Type Description Name Pin # P3.28 BLS3 Low-active Byte Lane Select signal (Bank 3). AIN7 A/D converter, input 7. This analog input is always connected to its pin.
Page 100: Pin Connect Block
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 8. PIN CONNECT BLOCK FEATURES • Allows individual pin configuration APPLICATIONS The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions. DESCRIPTION The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.
Page 101 The PINSEL0 register controls the functions of the pins as per the settings listed in Table 65. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 58: Pin Function Select Register 0 for LPC2119/2129 (PINSEL0 - 0xE002C000) Reset PINSEL0...
Page 102 The PINSEL1 register controls the functions of the pins as per the settings listed in following tables. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Table 61: Pin Function Select Register 1 for LPC2119/2129 (PINSEL1 - 0xE002C004) Reset PINSEL1...
Page 103 Warning: use read-modify-write operation when accessing PINSEL2 register. Accidental write of 0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Table 63: Pin Function Select Register 2 for LPC2119/2129 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value Reserved.
Page 104 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 64: Pin Function Select Register 2 for LPC2292/2294 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value Reserved. When 0, pins P1.36:26 are used as GPIO pins. When 1, P1.31:26 are used as a Debug port.
Page 105: Boot Control On 144-Pin Package
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 64: Pin Function Select Register 2 for LPC2292/2294 (PINSEL2 - 0xE002C014) PINSEL2 Description Reset Value BOOT1 during Controls whether P3.1/A1 is a port pin (0) or an address line (1). Reset Controls the number of pins among P3.23/A23/XCLK and P3.22:2/A2.22:2 that are address lines:...
Page 106: Gpio
REGISTER DESCRIPTION LPC2119/2129 has two 32-bit General Purpose I/O ports. Total of 30 out of 32 pins are available on PORT0. PORT1 has up to 16 pins available for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4 registers as shown in Table 68.
Page 107 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 68: GPIO Register Map PORT1 Generic PORT0 Address & Name Description Access Name Address & Name GPIO Port Pin value register. The current state of the port 0xE0028000 0xE0028010 IOPIN pins can always be read from this register, regardless of...
Page 108 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010) This register provides the value of the GPIO pins. This value reflects any outside world influence on the pins. Note: for test purposes, writing to this register stores the value in the output register, bypassing the need to use both the IOSET and IOCLR registers.
Page 109: Gpio Usage Notes
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 GPIO Direction Register (IO0DIR - 0xE0028008, IO1DIR - 0xE0028018) This register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality.
Page 110: Uart0
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 10. UART0 FEATURES • 16 byte Receive and Transmit FIFOs. • Register locations conform to ‘550 industry standard. • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. • Built-in baud rate generator.
Page 111: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION Table 74: UART0 Register Map Address Reset Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access Offset Value* Receiver 0xE000C000...
Page 112 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 75: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only) Reset U0RBR Function Description Value Receiver Buffer The UART0 Receiver Buffer Register contains the oldest received byte in the UART0 Rx Register FIFO.
Page 113 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART0 Interrupt Enable Register (U0IER - 0xE000C004 when DLAB = 0) The U0IER is used to enable the four UART0 interrupt sources. Table 79: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0)
Page 114 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 The UART0 RLS interrupt (U0IIR3:1=011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART0 Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART0 Rx error condition that set the interrupt can be observed via U0LSR4:1.
Page 115 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART0 FIFO Control Register (U0FCR - 0xE000C008) The U0FCR controls the operation of the UART0 Rx and Tx FIFOs. Table 82: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) Reset U0FCR...
Page 116 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART0 Line Control Register (U0LCR - 0xE000C00C) The U0LCR determines the format of the data character that is to be transmitted or received. Table 83: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C)
Page 117 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 84: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) Reset U0LSR Function Description Value 0: U0RBR is empty Receiver 1: U0RBR contains valid data Data Ready U0LSR0 is set when the U0RBR holds an unread character and is cleared when the (RDR) UART0 RBR FIFO is empty.
Page 118 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART0 Scratch Pad Register (U0SCR - 0xE000C01C) The U0SCR has no effect on the UART0 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.
Page 119: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE The architecture of the UART0 is shown below in the block diagram. The VPB interface provides a communications link between the CPU or host and the UART0. The UART0 receiver block, U0Rx, monitors the serial input line, RxD0, for valid input. The UART0 Rx Shift Register (U0RSR) accepts valid characters via RxD0.
Page 120: Figure 21: Uart0 Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 U0Tx NTXRDY TxD0 U0THR U0TSR U0BRG U0DLL NBAUDOUT U0DLM RCLK U0Rx NRXRDY INTERRUPT RxD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0] Interface pclk Figure 21: UART0 Block Diagram...
Page 121 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART0 January 08, 2004...
Page 122: Uart1
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 11. UART1 FEATURES • UART1 is identical to UART0, with the addition of a modem interface. • 16 byte Receive and Transmit FIFOs. • Register locations conform to ‘550 industry standard. • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Page 123: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION Table 87: UART1 Register Map Reset Address Name Description BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Access Value* Receiver 0xE0010000 U1RBR...
Page 124 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only) The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
Page 125 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 91: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1) Reset U1DLM Function Description Value Divisor Latch The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the MSB Register baud rate of the UART1.
Page 126 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Interrupt Identification Register (U1IIR - 0xE0010008, Read Only) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access.
Page 127 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 94: UART1 Interrupt Handling Interrupt Interrupt Interrupt U1IIR[3:0] Priority Type Source Reset 0001 none none Rx Line Status / 0110 Highest OE or PE or FE or BI U1LSR Read Error...
Page 128 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 FIFO Control Register (U1FCR - 0xE0010008) The U1FCR controls the operation of the UART1 Rx and Tx FIFOs. Table 95: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) Reset U1FCR Function Description Value Active high enable for both UART1 Rx and Tx FIFOs and U1FCR7:1 access.
Page 129 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Line Control Register (U1LCR - 0xE001000C) The U1LCR determines the format of the data character that is to be transmitted or received. Table 96: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C)
Page 130 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Modem Control Register (U1MCR - 0xE0010010) The U1MCR enables the modem loopback mode and controls the modem output signals. Table 97: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) Reset...
Page 131 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Line Status Register (U1LSR - 0xE0010014, Read Only) The U1LSR is a read-only register that provides status information on the UART1 Tx and Rx blocks. Table 98: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only)
Page 132 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Modem Status Register (U1MSR - 0x0xE0010018) The U1MSR is a read-only register that provides status information on the modem input signals. U1MSR3:0 is cleared on U1MSR read. Note that modem signals have no direct affect on UART1 operation, they facilitate software implementation of modem signal operations.
Page 133 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 UART1 Scratch Pad Register (U1SCR - 0xE001001C) The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U1SCR has occurred.
Page 134: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE The architecture of the UART1 is shown below in the block diagram. The VPB interface provides a communications link between the CPU or host and the UART1. The UART1 receiver block, U1Rx, monitors the serial input line, RxD1, for valid input. The UART1 Rx Shift Register (U1RSR) accepts valid characters via RxD1.
Page 135: Figure 22: Uart1 Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 MODEM U1Tx NTXRDY TxD1 U1THR U1TSR U1MSR U1BRG U1DLL NBAUDOUT U1MCR U1DLM RCLK U1Rx NRXRDY INTERRUPT RxD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0]...
Page 136: I2C Interface
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 12. I C INTERFACE FEATURES • Standard I C compliant bus interface. • Easy to configure as Master, Slave, or Master/Slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves.
Page 137: Figure 24: Slave Mode Configuration
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 C Bus Other Device with I Other Device with I LPC2119/2129 Interface Interface LPC2292/2294 Figure 23: I C Bus Configuration C Operating Modes Master Transmitter Mode: In this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, I2CONSET must be initialized as shown in Figure 24.
Page 138: Figure 25: Format In The Master Transmitter Mode
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 18h, 20h, or 38h for the master mode, or 68h, 78h, or 0B0h if the slave mode was enabled (by setting AA=1).
Page 139: Figure 27: A Master Receiver Switch To Master Transmitter After Sending Repeated Start
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 DATA DATA DATA Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) A = Not Acknowledge (SDA high) S = START condition P = STOP Condition From Master to Slave...
Page 140: Pin Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 DATA Slave Address DATA P/RS Data Transferred "0" - Write (n Bytes + Acknowledge) "1" - Read A = Acknowledge (SDA low) A = Not Acknowledge (SDA high) From Master to Slave...
Page 141: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The I C interface contains 7 registers as shown in Table 102. below. Table 102: I C Register Map Reset Address Name Description Access Value* 0xE001C000 I2CONSET I C Control Set Register...
Page 142 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 C Control Set Register (I2CONSET - 0xE001C000) AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 1.
Page 143 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 I2EN I C Interface Enable. When I2EN is 1, the I C function is enabled. I2EN can be cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I C function is disabled.
Page 144 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 C Status Register (I2STAT - 0xE001C004) This is a read-only register. It contains the status code of the I C interface. The least three bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and the SI bit is not set. All other 25 status codes correspond to defined I C states.
Page 145 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 C SCL Duty Cycle Registers (I2SCLH - 0xE001C010 and I2SCLL - 0xE001C014) Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate. I2SCLH defines the number of pclk cycles for SCL high, I2SCLL defines the number of pclk cycles for SCL low.
Page 146 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 111: I2C Clock Rate Selections for VPB Clock Divider = 2 Bit Frequency (kHz) At f (MHz) & VPB Clock Divider = 2 CCLK I2SCLL+ I2SCLH 320.0 400.0 160.0 200.0 400.0 106.667...
Page 147: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE I2ADR Address Register Comparator Input Filter Shift Register Output Stage I2DAT Bit Counter / Arbitration & pclk Sync Logic Input Filter Timing & Control Logic Interrupt Output Serial Clock Stage Generator I2CONSET Control Register &...
Page 148: Spi Interface
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 13. SPI INTERFACE FEATURES • Two complete and independent SPI cintrollers • Compliant with Serial Peripheral Interface (SPI) specification. • Synchronous, Serial, Full Duplex Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate.
Page 149: Figure 32: Spi Data Transfer Format (Cpha = 0 And Cpha = 1)
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 MOSI (CPHA = 0) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...
Page 150 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 When a device is a master, the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted. At this point, the master can activate the clock, and begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
Page 151 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave. This process assumes that any prior data transfer has already completed. It is required that the system clock driving the SPI logic be at least 8X faster than the SPI.
Page 152: Pin Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PIN DESCRIPTION Table 114: SPI Pin Description Pin Name Type Pin Description Serial Clock. The SPI is a clock signal used to synchronize the transfer of data across the SPI Input/ interface. The SPI is always driven by the master and received by the slave. The clock is...
Page 153: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The SPI contains 5 registers as shown in Table 115. All registers are byte, half word and word accessible. Table 115: SPI Register Map SPI0 SPI1 Generic Reset Address &...
Page 154 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004) The SPSR register controls the operation of the SPI as per the configuration bits setting. Table 117: SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004)
Page 155 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 The SPI rate may be calculated as: PCLK rate / SPCCR value. The pclk rate is CCLK / VPB divider rate as determined by the VPBDIV register contents. SPI Interrupt Register (S0SPINT - 0xE002001C, S1SPINT - 0xE003001C) This register contains the interrupt flag for the SPI interface.
Page 156: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE The block diagram of the SPI solution implemented in SPI0 and SPI1 interfaces is shown in the Figure 33. MOSI_in MOSI_out MISO_in MISO_out SPI Shift Register SCK_in SCK_out SS_in SPI Clock Generator &...
Page 157 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 SPI Interface January 08, 2004...
Page 158: Can Controllers And Acceptance Filter
Its domain of application ranges from high speed networks to low cost multiplex wiring. The LPC2119/2129/2292/2294 CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications.
Page 159: Can Controllers
CAN CONTROLLERS Each CAN Controller has a register structure similar to the Philips SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32 bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter.
Page 160 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 In the following register tables, the column “Reset Value” shows how a hardware reset affects each bit or field, while the column “RM Set” indicates how each bit or field is affected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note that while hardware reset sets RM, in this case the setting noted in the “Reset Value”...
Page 161 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Command Register (CANCMR - 0xE00x x004) Writing to this write-only register initiates an action. Bits not listed should be written as 0. Reading this register yields zeroes. Table 125: CAN Command Register (CANCMR - 0xE00x x004)
Page 162 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Global Status Register (CANGSR - 0xE00x x008) This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not listed read as 0 and should be written as 0.
Page 163 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 127: CAN Interrupt and Capture Register (CANICR - 0xE00x x00C) CANICR Name Function Reset Value RM Set 1: Receive Interrupt -- this bit is set whenever the RBS bit in CANSR and the RIE bit in CANIER are both 1, indicating that a received message is available.=.
Page 164 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Interrupt Enable Register (CANIER - 0xE00x x010) This read/write register controls whether various events on the CAN controller will result in an interrupt. Bits 7:0 in this register correspond 1-to-1 with bits 7:0 in the CANICR register.
Page 165 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Error Warning Limit Register (CANEWL - 0xE00x x018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time, but can only be written if the RM bit in CANmod is 1.
Page 166 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Rx Frame Status Register (CANRFS - 0xE00x x020) This register defines the characteristics of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1.
Page 167 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Rx Data Register A (CANRDA - 0xE00x x028) This register contains the first 1-4 Data bytes of the current received message. It is read-only in normal operation, but can be written for testing purposes if the RM bit in CANMOD is 1.
Page 168 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Tx Frame Information Register (CANTFI1, 2, 3 - 0xE00x x030, 40, 50) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the format of the next transmit message for that Tx buffer.
Page 169: Can Controller Operation
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Tx Data Register A (CANTDA1, 2, 3 - 0xE00x x038, 48, 58) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the first 1-4 Data bytes of the next transmit message.
Page 170 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Sleep Mode The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition.
Page 171: Centralized Can Registers
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CENTRALIZED CAN REGISTERS Three read-only registers group the bits in the Status registers of the CAN controllers for common accessibility. If devices with more or fewer CAN controllers are defined, the number of bits used in the active bytes will change correspondingly. Each defined byte of the following registers contains one particular status bit from each of the CAN controllers, in its LS bits.
Page 172: Figure 34: Entry In Fullcan And Individual Standard Identifier Tables
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Controller # Identifier able used Figure 34: Entry in fullCAN and Individual Standard Identifier Tables The table of Standard Identifier Ranges contains paired upper and lower (inclusive) bounds, one pair per word. These must also be arranged in ascending numerical order.
Page 173: Acceptance Filter Registers
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 controller. If it finds an equal match, the AF signals the CAN controller to retain the message, and provides it with an ID Index value to store in its the Receive Frame Status register register.
Page 174 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) Table 148: Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) EFF_sa Name Function Reset Value The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below.
Page 175: Examples Of Acceptance Filter Tables And Id Index Values
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 LUT Error Register (LUTerr - 0xE003 C01C) Table 152: LUT Error Register (LUTerr - 0xE003 C01C) LUTerr Name Function Reset Value This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM.
Page 176: Fullcan Mode
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Look-up Table RAM SFF_sa 0 d := 000 h := 0 0000 0000 b VPB BASE+ column_lower column_upper ID Index # Address 00d = 04d = 44d = 48d = 30h 52d =...
Page 177 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 1. The Standard Frame Individual Start Address Register (SFF_sa) must be greater than or equal to the number of IDs for which automatic receive storage is to be done, times two. SFF_sa must be rounded up to a multiple of 4 if necessary.
Page 178 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Start Read 1st word SEM == 01? This message has not been SEM == 11? received since last check. Clear SEM, write back 1st word Read 2nd and 3rd words Read 1st word...
Page 179 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CAN Controllers and Acceptance Filter January 08, 2004...
Page 180: Timer0 And Timer1
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 15. TIMER0 AND TIMER1 Timer0 and Timer1 are functionally identical except for the peripheral base address. FEATURES • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
Page 181: Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 DESCRIPTION The Timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.
Page 182: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION Each Timer contains the registers shown in Table 156. More detailed descriptions follow. Table 156: TIMER0 and TIMER1 Register Map TIMER0 TIMER1 Generic Reset Address & Address & Description Access...
Page 183 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000) The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.
Page 184 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Prescale Counter Register (PC: TIMER0 - T0PC: 0xE0004010; TIMER1 - T1PC: 0xE0008010) The 32-bit Prescale Counter controls division of pclk by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows.
Page 185 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.
Page 186 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 External Match Register (EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C) The External Match Register provides both control and status of the external match pins M(0-3). Table 161: External Match Register (EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C)
Page 187: Example Timer Operation
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 EXAMPLE TIMER OPERATION Figure 38 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value.
Page 188: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE The block diagram for TIMER0 and TIMER1 is shown in Figure 40. Match Register 0 Match Register 1 Match Register 2 Match Register 3 Match Control Register External Match Register Interrupt Register...
Page 189 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Timer0 and Timer1 January 08, 2004...
Page 190: Pulse Width Modulator (Pwm)
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2119/2129/2292/2294. The Timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
Page 191 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.
Page 192: Figure 41: Pwm Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Match Register 0 Shadow Register 0 Load Enable Match Register 1 Shadow Register 1 Load Enable Match Register 2 Shadow Register 2 Load Enable Match Register 3 Shadow Register 3 Load Enable...
Page 193: Figure 42: Sample Pwm Waveforms
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 A sample of how PWM values relate to waveform outputs is shown in Figure 42. PWM output logic is shown in Figure 41 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The match register selections for various PWM outputs is shown in Table 163.
Page 194 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Rules for Single Edge Controlled PWM Outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high.
Page 195: Pin Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PIN DESCRIPTION Table 164 gives a brief summary of each of PWM related pins. Table 164: Pin summary Pin name Pin direction Pin Description PWM1 Output Output from PWM channel 1. PWM2 Output Output from PWM channel 2.
Page 196: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The PWM function adds new registers and registers bits as shown in Table 165 below. Table 165: Pulse Width Modulator Register Map Reset Address Name Description Access Value* PWM Interrupt Register. The IR can be written to clear interrupts. The IR can...
Page 197 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 165: Pulse Width Modulator Register Map Reset Address Name Description Access Value* PWM Match Register 5. MR5 can be enabled through MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt when it matches the TC.
Page 198 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PWM Interrupt Register (PWMIR - 0xE0014000) The PWM Interrupt Register consists of eleven bits (Table 166), seven for the match interrupts and four reserved for the future use. If an interrupt is generated then the corresponding bit in the PWMIR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt.
Page 199 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PWM Timer Control Register (PWMTCR - 0xE0014004) The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each of the bits is shown in Table 167.
Page 200 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PWM Match Control Register (PWMMCR - 0xE0014014) The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter. The function of each of the bits is shown in Table 168.
Page 201 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 168: PWM Match Control Register (PWMMCR - 0xE0014014) Reset PWMMCR Function Description Value When one, the PWMTC and PWMPC will be stopped and PWMTCR[0] will be set to Stop on PWMMR5 0 if PWMMR5 matches the PWMTC.
Page 202 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 PWM Latch Enable Register (PWMLER - 0xE0014050) ThePWM Latch Enable Register is used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is held in a shadow register.
Page 203 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Pulse Width Modulator (PWM) January 08, 2004...
Page 204: A/D Converter
17. A/D CONVERTER FEATURES • 10 bit successive approximation analog to digital converter. • Input multiplexing among 4 pins (LPC2119/2129) or 8 pins (LPC2292/2294) • Power down mode • Measurement range 0 to 3 V • 10 bit conversion time >= 2.44 uS •...
Page 205 Description Reset Value Selects which of the Ain3:0 (LPC2119/2129) or Ain7:0 (LPC2292/2294) pins is (are) to be sampled and converted. Only bits 3:0 should be set to 1 in the 48 or 64 pin package. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any 0x01 value containing 1 to 8 ones (1 to 4 ones in the 48 or 64 pin package) can be used.
Page 206: Operation
Philips Semiconductors Preliminary User Manual LPC2119/2129/2292/2294 ARM-based Microcontroller A/D Data Register (ADDR - 0xE0034004) ADDR Name Description Reset Value This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read DONE and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
Page 207 Philips Semiconductors Preliminary User Manual LPC2119/2129/2292/2294 ARM-based Microcontroller A/D Converter January 08, 2004...
Page 208: Real Time Clock
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 18. REAL TIME CLOCK FEATURES • Measures the passage of time to maintain a calendar and clock. • Ultra Low Power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year.
Page 209: Architecture
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ARCHITECTURE clk32k Reference Clock Divider (Prescaler) Clock Generator Strobe Clk1 CCLK Time Comparators Alarm Counters Registers Counter Increment Counter Alarm Mask Enables Register Interrupt Enable Interrupt Generator Figure 43: RTC block diagram REGISTER DESCRIPTION The RTC includes a number of registers.
Page 210 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 175: Real Time Clock Register Map Reset Address Name Size Description Access Value 0xE0024000 Interrupt Location Register 0xE0024004 Clock Tick Counter. 0xE0024008 Clock Control Register 0xE002400C CIIR Counter Increment Interrupt Register...
Page 211: Rtc Interrupts
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 RTC INTERRUPTS Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register (AMR). Interrupts are generated only by the transition into the interrupt state. The ILR separately enables CIIR and AMR interrupts.
Page 212: Miscellaneous Register Group
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 MISCELLANEOUS REGISTER GROUP Table 176 summarizes the registers located from 0 to 7 of A[6:2]. More detailed descriptions follow. Table 176: Miscellaneous Registers Address Name Size Description Access Interrupt Location. Reading this location indicates the source of an 0xE0024000 interrupt.
Page 213 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Clock Control Register (CCR - 0xE0024008) The clock register is a 4-bit register that controls the operation of the clock divide circuit. Each bit of the clock register is described in Table 179.
Page 214 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 181: Alarm Mask Register Bits (AMR - 0xE0024010) Function Description AMRSEC When one, the Second value is not compared for the alarm. AMRMIN When one, the Minutes value is not compared for the alarm.
Page 215: Consolidated Time Registers
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 CONSOLIDATED TIME REGISTERS The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32-bit values as shown in Tables 182, 183, and 184.
Page 216 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Consolidated Time Register 2 (CTIME2 - 0xE002401C) The Consolidate Time Register 2 contains just the Day of Year value. Table 184: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) CTIME2 Function Description...
Page 217: Time Counter Group
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 TIME COUNTER GROUP The time value consists of the eight counters shown in Tables 185 and 186. These counters can be read or written at the locations shown in Table 186. Table 185: Time Counter Relationships and Values...
Page 218: Alarm Register Group
RTC was activated. No provision is made in the LPC2119/2129/2292/2294 to retain RTC status upon power loss, or to maintain time incrementation if the clock source is lost, interrupted, or altered. Loss of chip power will result in complete loss of all RTC register contents. Entry to Power Down mode will cause a lapse in the time update.
Page 219: Reference Clock Divider (Prescaler)
1. For frequencies that are expected to be supported by the LPC2119/2129/2292/2294, a 13-bit integer counter is required. This can be calculated as 160 MHz divided by 32,768 minus 1 = 4881 with a remainder of 26,624. Thirteen bits are needed to hold the value 4881, but actually supports frequencies up to 268.4 MHz (32,768 x 8192).
Page 220: Figure 44: Rtc Prescaler Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Example of Prescaler Usage In a simplistic case, the pclk frequency is 65.537 kHz. So: PREINT = int (pclk / 32768) - 1 = 1 and PREFRAC = pclk - ((PREINT +1) x 32768) = 1 With this prescaler setting, exactly 32,768 clocks per second will be provided to the RTC by counting 2 pclks 32,767 times, and 3 pclks once.
Page 221 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Prescaler Operation The Prescaler block labelled "Combination Logic" in Figure 44 determines when the decrement of the 13-bit PREINT counter is extended by one pclk. In order to both insert the correct number of longer cycles, and to distribute them evenly, the Combinatorial Logic associates each bit in PREFRAC with a combination in the 15-bit Fraction Counter.
Page 222: Watchdog
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 19. WATCHDOG FEATURES • Internally resets chip if not periodically reloaded • Debug mode • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled •...
Page 223: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The Watchdog contains 4 registers as shown in Table 192 below. Table 192: Watchdog Register Map Reset Address Name Description Access Value* Watchdog mode register. This register contains the basic mode and...
Page 224 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Watchdog Mode Register (WDMOD - 0xE0000000) The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits. WDEN WDRESET Debug/Operate without the Watchdog running Debug with the Watchdog interrupt but no WDRESET Operate with the Watchdog interrupt and WDRESET Once the WDEN and/or WDRESET bits are set they can not be cleared by software.
Page 225 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Watchdog Feed Register (WDFEED - 0xE0000008) Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer to the WDTC value. This operation will also start bit in the WDMOD register is not sufficient to the Watchdog if it is enabled via the WDMOD register.
Page 226: Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 BLOCK DIAGRAM The block diagram of the Watchdog is shown below in the Figure 45. FEED ERROR FEED WDTC SEQUENCE FEED OK WDFEED UNDER FLOW 32-BIT DOWN pclk COUNTER ENABLE COUNT WDTV...
Page 227 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Watchdog January 08, 2004...
Page 228: Flash Memory System And Programming
The Flash Memory System contains 16 sectors for 128 kB part and 17 sectors for 256 kB part. Flash memory begins at address 0 and continues upward. Details may be found in the LPC2119/2129/2292/2294 Memory Addressing chapter. FLASH BOOT LOADER The Boot Loader controls initial operation after reset, and also provides the means to accomplish programming of the Flash memory.
Page 229: Figure 46: Map Of Lower Memory After Any Reset (128 Kb Flash Part)
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 The flash boot loader is designed to run from this memory area but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is described later in this chapter. The interrupt vectors residing in the boot sector of the on-chip flash memory also become active after reset i.e.
Page 230 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ISP Command Format "Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Applicable only in case of Write commands) ISP Response Format "Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ... Response_n<CR><LF>" "Data" (Applicable in case of Read commands) ISP Data Format The data stream is in UU-encode format.
Page 231 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 RAM used by RealMonitor The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. The user could use this area if RealMonitor based debug is not required. The Flash boot loader does not initialize the stack for the RealMonitor.
Page 232: Boot Process Flowchart
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 BOOT PROCESS FLOWCHART Reset Initialize WatchDog Flag Set? User Code Valid? Enter ISP Mode? (P0.14 LOW?) Execute User code Run Auto-Baud Auto-Baud Successful? Receive crystal frequency Run ISP Command Handler Figure 47: Boot Process flowchart...
Page 233: Sector Numbers
Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicates the correspondence between sector numbers and memory addresses for LPC2119/2129/2292/2294 device(s). IAP, ISP and RealMonitor routines are located in the Boot Sector. The boot sector is present in all devices. ISP and IAP commands do not allow write/erase/go operation on the boot sector.
Page 234 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ISP Commands The following commands are accepted by the ISP command handler. Detailed return codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 235 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Set Baud Rate <Baud Rate> <stop bit> Table 199: ISP Set Baud Rate command description Command Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400 Input Stop bit: 1 | 2...
Page 236 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Write to RAM <start address> <number of bytes> The host should send the data only after receiving the CMD_SUCCESS return code. The host should send the check-sum after transmitting 20 UU-encoded lines. The length of any UU-encoded line should not exceed 61 characters(bytes) i.e. it can hold 45 data bytes.
Page 237 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. Table 204: ISP Prepare sector(s) for write operation command description Command...
Page 238 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Go <address> <Mode> Table 206: ISP Go command description Command Address: Flash or RAM address from which the code execution is to be started. This address should Input be on a word boundary.
Page 239 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Blank check sector(s) <start sector number> <end sector number> Table 208: ISP Blank check sector(s) command description Command Start Sector Number Input End Sector Number: Should be greater than or equal to start sector number.
Page 240 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Compare <address1> <address2> <number of bytes> Table 211: ISP Compare command description Command Address1(DST): Starting Flash or RAM address from where data bytes are to be compared. This address should be on word boundary.
Page 241 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Table 212: ISP Return Codes Summary Return Mnemonic Description Code Command is executed successfully. Sent by ISP CMD_SUCCESS handler only when command given by the host has been completely and successfully executed.
Page 242 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 IAP Commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1.
Page 243 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 0x7fffffb0 A rm_prefetchabort_handler 0x7fffffc0 A rm_dataabort_handler 0x7fffffd0 A rm_irqhandler 0x7fffffe0 A rm_irqhandler2 0x7ffffff0 T iap_entry As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively.
Page 244: Figure 48: Iap Parameter Passing
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Command Code Command Parameter 0 parameter table Parameter 1 ARM Register r0 ARM Register r1 Parameter n Status Code Command Result 0 result table Result 1 Result n Figure 48: IAP Parameter passing Prepare sector(s) for write operation This command makes flash write/erase operation a two step process.
Page 245 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Copy RAM to Flash Table 215: IAP Copy RAM to Flash command description Command Copy RAM to Flash Command code: 51 Param0(DST): Destination Flash address where data bytes are to be written. The destination address should be a 512 byte boundary.
Page 246 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Blank check sector(s) Table 217: IAP Blank check sector(s) command description Command Blank check sector(s) Command code: 53 Input Param0: Start Sector Number Param1: End Sector Number: Should be greater than or equal to start sector number.
Page 247 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Compare Table 220: IAP Compare command description Command Compare Command Code: 56 Param0(DST): Starting Flash or RAM address from where data bytes are to be compared. This address should be a word boundary.
Page 248: Jtag Flash Programming Interface
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 JTAG FLASH PROGRAMMING INTERFACE Debug tools can write parts of the flash image to the RAM and then execute the IAP call "Copy RAM to Flash" repeatedly with proper offset. Flash Memory System and Programming...
Page 249 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Flash Memory System and Programming January 08, 2004...
Page 250: Embeddedice Logic
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 21. E ICE LOGIC MBEDDED FEATURES • No target resources are required by the software debugger in order to start the debugging session • Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly to the core •...
Page 251: Pin Description
RESET STATE OF MULTIPLEXED PINS On the LPC2119/2129/2292/2294, the pins above are multiplexed with P1.31-26. To have them come up as a Debug port, connect a weak bias resistor (4.7 kΩ) between VSS and the P1.26/RTCK pin. To have them come up as GPIO pins, do not connect a bias resistor, and ensure that any external driver connected to P1.26/RTCK is either driving high, or is in high-...
Page 252: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The EmbeddedICE logic contains 16 registers as shown in Table 223. below. The ARM7TDMI-S debug architecture is described in detail in "ARM7TDMI-S (rev 4) Technical Reference Manual" (ARM DDI 0234A) published by ARM Limited and is available via Internet at http://www.arm.com.
Page 253: Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 BLOCK DIAGRAM The block diagram of the debug environment is shown below in Figure 49. JTAG PORT Serial/ Parallel EmbeddedICE Interface Interface EmbeddedICE Protocol Converter HOST RUNNING ARM7TDMI-S DEBUGGER TARGET BOARD Figure 49: EmbeddedICE Debug Environment Block Diagram...
Page 254: Embedded Trace Macrocell
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 22. EMBEDDED TRACE MACROCELL FEATURES • Closely track the instructions that the ARM core is executing • 10 pin interface • 1 External trigger input • All registers are programmed through JTAG interface •...
Page 255: Pin Description
External Trigger Input. RESET STATE OF MULTIPLEXED PINS On the LPC2119/2129/2292/2294, the ETM pin functions are multiplexed with P1.25-16. To have these pins come as a Trace port, connect a weak bias resistor (4.7 kΩ ) between the P1.20/TRACESYNC pin and V .
Page 256: Register Description
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REGISTER DESCRIPTION The ETM contains 29 registers as shown in Table 226. below. They are described in detail in the ARM IHI 0014E document published by ARM Limited, which is available via the Internet at http://www.arm.com.
Page 257: Block Diagram
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 BLOCK DIAGRAM The block diagram of the ETM debug environment is shown below in Figure 50. PERIPHERAL TRACE TRACE PORT ANALYZER TRIGGER PERIPHERAL CONNECTOR HOST JTAG RUNNING INTERFACE DEBUGGER EmbeddedICE UNIT CONNECTOR...
Page 258: Realmonitor
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 23. REALMONITOR RealMonitor is a configurable software module which enables real time debug. RealMonitor is developed by ARM Inc. Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide (ARM DUI 0142A). It applies to a specific configuration of RealMonitor software programmed in the on-chip flash memory of this device.
Page 259: Figure 51: Realmonitor Components
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 RealMonitor Components As shown in Figure 51, RealMonitor is split in to two functional components: RMHost This is located between a debugger and a JTAG unit. The RMHost controller, , converts generic Remote Debug RealMonitor.dll...
Page 260: Figure 52: Realmonitor As A State Machine
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 How RealMonitor works In general terms, the RealMonitor operates as a state machine, as shown in Figure 52. RealMonitor switches between running and stopped states, in response to packets received by the host, or due to asynchronous events on the target. RMTarget supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at a time.
Page 261 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 • RealMonitor enters a loop, polling the DCC. If the DCC read buffer is full, control is passed to (RealMonitor rm_ReceiveData() internal function). If the DCC write buffer is free, control is passed to (RealMonitor internal function).
Page 262: How To Enable Realmonitor
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 HOW TO ENABLE REALMONITOR The following steps must be performed to enable RealMonitor. A code example which implements all the steps can be found at the end of this section. Adding stacks User must ensure that stacks are set up within application for each of the processor modes used by RealMonitor.
Page 263: Figure 53: Exception Handlers
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and user application. RealMonitor exception handling To function properly, RealMonitor must be able to intercept certain interrupts and exceptions. Figure 53 illustrates how exceptions can be claimed by RealMonitor itself, or shared between RealMonitor and application.
Page 264 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 RMTarget initialization While the processor is in a privileged mode, and IRQs are disabled, user must include a line of code within the start-up sequence of application to call rm_init_entry(). RealMonitor January 08, 2004...
Page 265 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 Code Example The following example shows how to setup stack, VIC, initialize RealMonitor and share non vectored interrupts: IMPORT rm_init_entry IMPORT rm_prefetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry ;Entry point of user application.
Page 266 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ; Initialize the IRQ mode stack for RealMonitor and User r1, r0, #0x1f r1, r1, #0x12 CPSR_c, r1 ;Keep 32 bytes for Abort mode stack SUB sp,r2,#0x7F ; Return to the original mode.
Page 267 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 ;MSR spsr, r12 ;Restore SPSR from r12 ;STMFD sp!, {r0} ;LDR r0, =VICBaseAddr ;STR r1, [r0,#VICVectAddrOffset] ;Acknowledge Non Vectored irq has finished ;LDMFD sp!, {r12,r14,r0} ;Restore registers ;SUBS pc, r14, #4 ;Return to the interrupted instruction ;user interrupt did not happen so call rm_irqhandler2.
Page 268: Realmonitor Build Options
Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 REALMONITOR BUILD OPTIONS RealMonitor was built with the following options: RM_OPT_DATALOGGING=FALSE This option enables or disables support for any target-to-host packets sent on a non RealMonitor (third-party) channel. RM_OPT_STOPSTART=TRUE This option enables or disables support for all stop and start debugging features.
Page 269 Philips Semiconductors Preliminary User Manual ARM-based Microcontroller LPC2119/2129/2292/2294 "execute code" buffer size. Also refer to RM_OPT_EXECUTECODE option. RM_OPT_GATHER_STATISTICS=FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor. RM_DEBUG=FALSE This option enables or disables additional debugging and error-checking code in RealMonitor.

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