Philips LPC2148 Manuals

Manuals and User Guides for Philips LPC2148. We have 1 Philips LPC2148 manual available for free PDF download: User Manual

Philips LPC2148 User Manual (348 pages)

Brand: Philips | Category: Microcontrollers | Size: 9.98 MB

Chapter 1: General Information

3
Introduction

3
Features

3
Applications

4
Device Information

4
Architectural Overview

4
Chapter 25 : Supplementary Information

5
ARM7TDMI-S Processor

5
On-Chip Flash Memory System

6
On-Chip Static RAM (SRAM)

6
Block Diagram

7
Chapter 2: LPC2141/2/4/6/8 Memory Addressing

8
Memory Maps

8
LPC2141/2142/2144/2146/2148 Memory Re-Mapping and Boot Block

11
- Memory Map Concepts and Operating Modes 11 Memory Re-Mapping
  12
Prefetch Abort and Data Abort Exceptions

15
Chapter 3: System Control Block

16
Summary of System Control Block Functions

16
Pin Description

16
Register Description

17
Crystal Oscillator

18
External Interrupt Inputs

20
Other System Controls

26
- System Control and Status Flags Register (SCS - 0Xe01F C1A0)
  26
Memory Mapping Control

26
- Memory Mapping Control Register
  26
  - 0Xe01F C040)
    26
- Memory Mapping Control Usage Notes
  27
Phase Locked Loop (PLL)

27
Power Control

35
Reset

38
- Reset Source Identification Register (RSIR - 0Xe01F C180)
  39
VPB Divider

40
- Register Description
  40
- VPBDIV Register (VPBDIV - 0Xe01F C100)
  40
Wakeup Timer

41
Brown-Out Detection

42
Code Security Vs. Debugging

43
Chapter 4: Memory Acceleration Module (MAM)

44
Introduction

44
Operation

44
MAM Blocks

45
MAM Operating Modes

46
MAM Configuration

47
Register Description

47
MAM Control Register

48
MAM Timing Register

48
MAM Usage Notes

49
Chapter 5: Vectored Interrupt Controller (VIC)

50
Features

50
Description

50
Register Description

50
VIC Registers

52
Interrupt Sources

59
Spurious Interrupts

61
VIC Usage Notes

63
Chapter 6 : Pin Configuration

66
LPC2141/2142/2144/2146/2148 Pinout

66
Pin Description for LPC2141/2/4/6/8

68
Chapter 7 : Pin Connect Block

75
Features

75
Applications

75
Description

75
Register Description

75
Chapter 8: General Purpose Input/Output Ports (GPIO)

81
Features

81
Applications

81
Pin Description

81
Register Description

81
GPIO Usage Notes

92
- Example 1: Sequential Accesses to IOSET and IOCLR Affecting the same GPIO Pin/Bit
  92
  - Example 2: an Immediate Output of 0S and 1S on a GPIO Port
    92
- Writing to IOSET/IOCLR .Vs. IOPIN
  93
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)

95
Features

95
Pin Description

95
Register Description

95
Architecture

109
Chapter 10 : Universal Asynchronous Receiver/Transmitter 1 (UART1)

112
Features

112
Pin Description

112
Register Description

113
Architecture

131
Chapter 11: I 2 C Interfaces I 2 C0 and I 2 C1

133
Features

133
Applications

133
Description

133
Pin Description

134
I 2 C Operating Modes

134
- Master Transmitter Mode
  134
- Master Receiver Mode
  135
- Slave Receiver Mode
  136
- Slave Transmitter Mode
  137
I 2 C Implementation and Operation

138
- Input Filters and Output Stages
  138
- Address Register, I2ADDR
  140
- Comparator
  140
- Shift Register, I2DAT
  140
- Arbitration and Synchronization Logic
  140
- Serial Clock Generator
  141
- Timing and Control
  141
- Control Register, I2CONSET and I2CONCLR
  141
- Status Decoder and Status Register
  142
Register Description

142
Details of I C Operating Modes

147
- Master Transmitter Mode
  148
- Master Receiver Mode
  148
- Slave Receiver Mode
  149
- Slave Transmitter Mode
  153
- Miscellaneous States
  159
- I2STAT = 0Xf8
  159
- I2STAT = 0X00
  159
- Some Special Cases
  160
- Simultaneous Repeated START Conditions from Two Masters
  160
- Data Transfer after Loss of Arbitration
  160
- Forced Access to the I C-Bus
  160
- C-Bus Obstructed by a Low Level on SCL or SDA
  161
- Bus Error
  161
  - C State Service Routines
    162
- Initialization
  163
- C Interrupt Service
  163
  - The State Service Routines
    163
- Adapting State Services to an Application
  163
Software Example

163
- Initialization Routine
  163
- Start Master Transmit Function
  163
- Start Master Receive Function
  164
- I 2 C Interrupt Routine
  164
- Non Mode Specific States
  164
- State: 0X00
  164
- Master States
  164
- State: 0X08
  164
- State: 0X10
  165
- Master Transmitter States
  165
- State: 0X18
  165
- State: 0X20
  165
- State: 0X28
  165
- State: 0X30
  166
- State: 0X38
  166
- Master Receive States
  166
- State: 0X40
  166
- State: 0X48
  166
- State: 0X50
  167
- State: 0X58
  167
- Slave Receiver States
  167
- State: 0X60
  167
- State: 0X68
  167
- State: 0X70
  168
- State: 0X78
  168
- State: 0X80
  168
- State: 0X88
  168
- State: 0X90
  169
- State: 0X98
  169
- State: 0Xa0
  169
- Slave Transmitter States
  169
- State: 0Xa8
  169
- State: 0Xb0
  169
- State: 0Xb8
  170
- State: 0Xc0
  170
- State: 0Xc8
  170
Chapter 12: SPI Interface (SPI0)

171
Features

171
Description

171
- SPI Overview
  171
- SPI Data Transfers
  171
- General Information
  173
- Master Operation
  173
- Slave Operation
  174
- Exception Conditions
  174
- Read Overrun
  174
- Write Collision
  174
- Mode Fault
  175
- Slave Abort
  175
Pin Description

175
Register Description

175
Architecture

179
Chapter 13: SSP Controller (SPI1)

180
Features

180
Description

180
Bus Description

181
Register Description

188
Chapter 14: USB Device Controller

194
Introduction

194
Features

195
Fixed Endpoint Configuration

195
Architecture

196
Data Flow

197
- Data Flow from USB Host to the Device
  197
- Data Flow from Device to the Host
  197
- Slave Mode Transfer
  197
- DMA Mode Transfer (LPC2146/8 Only)
  198
Interfaces

198
- Software Interface
  198
- Register Map
  198
USB Device Register Definitions

200
EP_RAM Requirements

209
Protocol Engine Command Description

222
- Set Address
  223
  - (Command: 0Xd0, Data: Write 1 Byte)
    223
- Configure Device (Command: 0Xd8, Data: Write 1 Byte)
  223
- Set Mode
  224
  - (Command: 0Xf3, Data: Write 1 Byte)
    224
Read Current Frame Number (Command: 0Xf5, 14.11 Data: Read 1 or 2 Bytes)

225
DMA Descriptor

230
- Next_Dd_Pointer
  231
- Dma_Mode
  232
- Next_Dd_Valid
  232
- Isochronous_Endpoint
  232
- Max_Packet_Size
  232
- Dma_Buffer_Length
  232
- Dma_Buffer_Start_Addr
  232
- Dd_Retired
  232
- Dd_Status
  232
- Packet_Valid
  233
- Ls_Byte_Extracted
  233
- Ms_Byte_Extracted
  233
- Present_Dma_Count
  233
- Message_Length_Position
  233
- Isochronous_Packetsize_Memory_Address
  233
DMA Operation

234
- Triggering the DMA Engine
  234
- Arbitration between Endpoints
  234
Non Isochronous Endpoints - Normal Mode Operation

234
- Setting up DMA Transfer
  234
- Finding DMA Descriptor
  234
- Transferring the Data
  235
- Optimizing Descriptor Fetch
  235
- Ending the Packet Transfer
  236
- No_Packet DD
  236
Concatenated Transfer (ATLE) Mode Operation

236
- Setting up the DMA Transfer
  239
- Finding the DMA Descriptor
  239
- Transferring the Data
  239
- Ending the Packet Transfer
  239
Isochronous Endpoint Operation

240
- Setting up of DMA Transfer
  240
- Finding the DMA Descriptor
  240
- Transferring the Data
  240
- Isochronous out Endpoint Operation Example
  241
Chapter 15 : Timer/Counter TIMER0 and TIMER1

242
Features

242
Applications

242
Description

242
Pin Description

242
Register Description

243
Example Timer Operation

251
Architecture

252
Chapter 16: Pulse Width Modulator (PWM)

253
Features

253
Description

253
- Rules for Single Edge Controlled PWM Outputs
  256
- Rules for Double Edge Controlled PWM Outputs
  257
Pin Description

257
Register Description

257
Chapter 17: Analog-To-Digital Converter (ADC)

265
Features

265
Description

265
Pin Description

265
Register Description

266
Operation

272
- Hardware-Triggered Conversion
  272
- Interrupts
  272
  - Accuracy Vs. Digital Receiver
    272
Chapter 18 : Digital-To-Analog Converter (DAC)

273
Features

273
Pin Description

273
DAC Register (DACR - 0Xe006 C000)

273
Operation

274
Features

275
Description

275
Architecture

275
Register Description

276
RTC Usage Notes

282
Reference Clock Divider (Prescaler)

282
RTC External 32 Khz Oscillator Component Selection

285
Chapter 20: Watchdog Timer

287
Features

287
Applications

287
Description

287
Register Description

288
Block Diagram

289
Chapter 21: Flash Memory System and Programming

291
Flash Boot Loader

291
Features

291
Applications

291
Description

291
- Memory Map after any Reset
  291
- Criterion for Valid User Code
  292
- Communication Protocol
  293
- ISP Command Format
  293
- ISP Response Format
  293
- ISP Data Format
  293
- ISP Flow Control
  293
- ISP Command Abort
  294
- Interrupts During ISP
  294
- Interrupts During IAP
  294
- RAM Used by ISP Command Handler
  294
- RAM Used by IAP Command Handler
  294
- RAM Used by Realmonitor
  294
- Boot Process Flowchart
  295
Sector Numbers

295
Flash Content Protection Mechanism

296
Code Read Protection (CRP)

297
ISP Commands

297
IAP Commands

305
- Prepare Sector(S) for Write Operation
  307
- Copy RAM to Flash
  308
- Erase Sector(S)
  308
- Blank Check Sector(S)
  309
- Read Part Identification Number
  309
- Read Boot Code Version Number
  309
- Compare <Address1> <Address2> <No of Bytes
  310
- Reinvoke ISP
  310
- IAP Status Codes
  310
JTAG Flash Programming Interface

311
Chapter 22: Embeddedice Logic

312
Features

312
Applications

312
Description

312
Pin Description

313
Reset State of Multiplexed Pins

313
Register Description

314
Block Diagram

314
Chapter 23: Embedded Trace Macrocell (ETM)

315
Features

315
Applications

315
Description

315
- ETM Configuration
  315
Pin Description

316
Reset State of Multiplexed Pins

316
Register Description

317
Block Diagram

318
Chapter 24: Realmonitor

319
Features

319
Applications

319
Description

319
- Realmonitor Components
  320
- Rmhost
  320
- Rmtarget
  320
- How Realmonitor Works
  321
How to Enable Realmonitor

322
- Adding Stacks
  322
- IRQ Mode
  322
- Undef Mode
  322
- SVC Mode
  322
- Prefetch Abort Mode
  323
- Data Abort Mode
  323
- User/System Mode
  323
- FIQ Mode
  323
- Handling Exceptions
  323
- Realmonitor Exception Handling
  323
- Rmtarget Initialization
  324
- Code Example
  324
Realmonitor Build Options

327

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Philips LPC2148 Manuals

Philips LPC2148 User Manual (348 pages)

Table of Contents

Chapter 1: General Information

Introduction

Features

Applications

Device Information

Architectural Overview

Chapter 25 : Supplementary Information

ARM7TDMI-S Processor

On-Chip Flash Memory System

On-Chip Static RAM (SRAM)

Block Diagram

Chapter 2: LPC2141/2/4/6/8 Memory Addressing

Memory Maps

LPC2141/2142/2144/2146/2148 Memory Re-Mapping and Boot Block

Prefetch Abort and Data Abort Exceptions

Chapter 3: System Control Block

Summary of System Control Block Functions

Pin Description

Register Description

Crystal Oscillator

External Interrupt Inputs

Other System Controls

Memory Mapping Control

Phase Locked Loop (PLL)

Power Control

Reset

VPB Divider

Wakeup Timer

Brown-Out Detection

Code Security Vs. Debugging

Chapter 4: Memory Acceleration Module (MAM)

Introduction

Operation

MAM Blocks

MAM Operating Modes

MAM Configuration

Register Description

MAM Control Register

MAM Timing Register

MAM Usage Notes

Chapter 5: Vectored Interrupt Controller (VIC)

Features

Description

Register Description

VIC Registers

Interrupt Sources

Spurious Interrupts

VIC Usage Notes

Chapter 6 : Pin Configuration

LPC2141/2142/2144/2146/2148 Pinout

Pin Description for LPC2141/2/4/6/8

Chapter 7 : Pin Connect Block

Features

Applications

Description

Register Description

Chapter 8: General Purpose Input/Output Ports (GPIO)

Features

Applications

Pin Description

Register Description

GPIO Usage Notes

Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)

Features

Pin Description

Register Description

Architecture

Chapter 10 : Universal Asynchronous Receiver/Transmitter 1 (UART1)

Features

Pin Description

Register Description

Architecture

Chapter 11: I 2 C Interfaces I 2 C0 and I 2 C1

Features

Applications

Description

Pin Description