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Philips Semiconductors
Table 77:
Bit Symbol
3
4
5
6
7
2
12.4 I
This is a read-only register. It contains the status code of the I
bits are always 0. There are 26 possible status codes. When the code is F8H, there is no
relevant information available and SI bit is not set. All other 25 status codes correspond to
defined I
Table 83
Table 78:
Bit
Symbol
Reset
Table 79:
Bit Symbol
0:2 -
3:7 STA[0:4] I
2
12.5 I
When the internal SCL generator is selected for the I
the I2CON register, the user must set values for registers I2SCLL and I2SCLH to select
the data rate. I2SCLH defines the number of PCLK cycles for SCL = high, I2SCLL defines
the number of PCLK cycles for SCL = low. The frequency is determined by the following
formula:
Where f
User manual
2
I
C Control register (I2CON - address D8h) bit description
Description
2
SI
I
C Interrupt Flag. This bit is set when one of the 25 possible I
When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI
is set. Must be cleared by software by writing 0 to this bit.
STO
STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the
2
I
C-bus. When the bus detects the STOP condition, it will clear STO bit
automatically. In slave mode, setting this bit can recover from an error condition. In
this case, no STOP condition is transmitted to the bus. The hardware behaves as if
a STOP condition has been received and it switches to 'not addressed' Slave
Receiver Mode. The STO flag is cleared by hardware automatically.
STA
Start Flag. STA = 1: I
START condition if the bus is free. If the bus is not free, it waits for a STOP
condition (which will free the bus) and generates a START condition after a delay
of a half clock period of the internal clock generator. When the I
already in master mode and some data is transmitted or received, it transmits a
repeated START condition. STA may be set at any time, it may also be set when
2
the I
C interface is in an addressed slave mode. STA = 0: no START condition or
repeated START condition will be generated.
2
I2EN
I
C Interface Enable. When set, enables the I
function is disabled.
-
reserved
C Status register
2
C states. When any of these states entered, the SI bit will be set. Refer to
to
Table 86
for details.
2
I
C Status register (I2STAT - address D9h) bit allocation
7
6
STA.4
STA.3
0
0
2
I
C Status register (I2STAT - address D9h) bit description
Description
Reserved, are always set to 0.
2
C Status code.
C SCL duty cycle registers I2SCLH and I2SCLL
Bit Frequency = f
/ (2*(I2SCLH + I2SCLL))
PCLK
is the frequency of PCLK.
PCLK
Rev. 03 — 7 June 2005
2
C-bus enters master mode, checks the bus and generates a
5
4
3
STA.2
STA.1
STA.0
0
0
0
2
C interface by setting CRSEL = 0 in
UM10119
P89LPC938 User manual
...continued
2
C states is entered.
2
C interface is
2
C interface. When clear, the I
2
C interface. The least three
2
1
0
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
C
0
0
0
79 of 139
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