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Philips Semiconductors
2
I
C INTERFACE
2
I
C Data register
I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while
it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2DAT remains
stable as long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit
7), and after a byte has been received, the first bit of received data is located at the MSB of I2DAT.
.
I2DAT
Address: DAH
Not bit addressable
Reset Source(s): Any reset
Reset Value: 00000000B
2
I
C Slave Address register
I2ADR register is readable and writable, and is only used when the I
register has no effect. The LSB of I2ADR is general call bit. When this bit is set, the general call address (00h) is recognized.
I2ADR
Address: DBH
Not bit addressable
Reset Source(s): Any reset
Reset Value: 00000000B
BIT
SYMBOL
I2ADR7, 1
I2ADR.6, 0
I2ADR7.0
GC
2
I
C Control register
The CPU can read and write this register. There are two bits are affected by hardware: the SI bit and the STO bit. The SI bit is
set by hardware and the STO bit is cleared by hardware.
CRSEL determines the SCL source when the I
automatically synchronize with any clock frequency up to 400 kHz from the master I
interface uses the Timer1 overflow rate divided by 2 for the I
auto-reload mode (Mode 2).
2
Data rate of I
C = Timer overflow rate / 2 = PCLK / (2*(256-reload value)),
If fosc = 12 MHz, reload value is 0 - 255, so I
2
When CRSEL = 0, the I
C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register. The
duty cycle does not need to be 50%.
2003 Dec 8
7
6
I2DAT.7
I2DAT.6
I2DAT.5
2
Figure 2: I
C Data register
7
6
I2ADR.6
I2ADR.5
I2ADR.4
FUNCTION
7 bit own slave address. When in master mode, the contents of this register has no effect.
General call bit. When set, the general call address (00H) is recognized, otherwise it is
ignored.
2
Figure 3: I
C Slave Address register
2
C is in master mode. In slave mode this bit is ignored and the bus will
2
C clock rate. Timer 1 should be programmed by the user in 8 bit
2
C data rate range is 11.72 Kbit/sec - 3000 Kbit/sec.
5
4
3
I2DAT.4
I2DAT.3
2
C interface is set to slave mode. In master mode, this
5
4
3
I2ADR.3
I2ADR.2
2
C device. When CRSEL = 1, the I
64
User's Manual - Preliminary -
P89LPC920/921/922
2
1
0
I2DAT.2
I2DAT.1
I2DAT.0
2
1
0
I2ADR.1
I2ADR.0
GC
2
C
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