Access Target Cpu Setting Status Area - Mitsubishi Electric Melsec Q Series User Manual

3
SPECIFICATIONS

3.6.9 Access target CPU setting status area

(1) Access target CPU setting information (Buffer memory address: 4000 to 4003)
(a) The information on whether [Access target CPU settings] have been made or not
(b) The bit corresponding to the preset Access target CPU setting No. is turned ON.
Buffer memory address: 4000
(2) Access target CPU error information (Buffer memory address: 4004 to 4007)
(a) The access target CPU error information is stored.
(b) The bit corresponding to the Access target CPU setting number for which the
Buffer memory address: 4004
(c) The following results when the Access target CPU error occurs.
(3) Access target CPU 1 to 64, error codes (Buffer memory address: 4008 to
4071)
The error code showing the error contents is stored in the corresponding area of
access target CPU setting number for which the Access target CPU error has
occurred.
For error codes, refer to the following:
is stored.
0: Not set
1: Set
b15 b14
16 15
4001 32 31
4002 48 47
4003 64 63
Figure 3.14 Access target CPU setting information area
Access target CPU error has occurred is turned ON.
0: No Access target CPU error
1: Access target CPU error occurred
b15 b14
16 15
4005 32 31
4006 48 47
4007 64 63
Figure 3.15 Access target CPU error information area
(Example) When an error occurred in the access target CPU for Access target
CPU setting No. 16
• Access target CPU error (X16) is turned ON.
• Access target CPU error information area (Buffer memory address: 4004 (bit
15)) is turned ON.
• The error code is stored in the Access target CPU 16, error code area (Buffer
memory address: 4023).
Section 10.2 Error Code List
b13 b12 b11 b10 b9 b8 b7
14 13 12 11 10 9 8
30 29 28 27 26 25 24
46 45 44 43 42 41 40
62 61 60 59 58 57 56
b13 b12 b11 b10 b9 b8 b7
14 13 12 11 10 9 8
30 29 28 27 26 25 24
46 45 44 43 42 41 40
62 61 60 59 58 57 56
3.6 Buffer Memory Details
3.6.9 Access target CPU setting status area
b6 b5 b4 b3 b2 b1 b0
7 6 5 4 3 2 1
23 22 21 20 19 18 17
39 38 37 36 35 34 33
55 54 53 52 51 50 49
b6 b5 b4 b3 b2 b1 b0
7 6 5 4 3 2 1
23 22 21 20 19 18 17
39 38 37 36 35 34 33
55 54 53 52 51 50 49
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