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3.6 Example of a PCI PIO Sliding Window Operation for RFM-5565
PCI PIO
Window
Default
64 MByte
16 MByte
2 MByte
RFM‐5565 cards are currently available with 128 or 256 MByte of installed
memory. Under some circumstances, it is useful to reduce the PCI memory
address space window size. For example, a BIOS may have difficulty dividing the
address space into enough windows with appropriate granularity for all of the
installed devices. In another example, the operating system may not be able to
assign resources for all of the drivers loaded. Reducing the PCI window size
allows the RFM‐5565 to use a smaller footprint on the PCI bus address space.
However, changing the PCI PIO window size does not affect other functions of
the card. All of the installed memory on the card can be updated by data packets
on the Reflective Memory network. For example, a 256 MByte card will reflect
every value written in the 256 MByte Reflective Memory network address space.
Also, the RFM‐5565 DMA engine can be used to access every byte of the memory
installed on the card. It is also possible to move (remap) the PCI PIO window to
access every byte of the memory installed on the card using PIO accesses.
Here is a brief description of selecting the PCI memory window size. There are
four possible choices: 2 MByte, 16 MByte, 64 MByte or use the default full
memory size. Two switches on S1 are used to configure the PCI memory window
size. The switch settings should only be changed while the power is off. Use S1
switch positions 3 and 4 to select one of the four window sizes. Bits 20 and 21 of
RFM register LCSR1 (PCIBAR2 Offset $08) indicate the full installed memory size.
Bit 19 of LCSR1 is connected to S1 switch position 3 and bit 22 of LCSR1 is
connected to S1 switch position 4. Both bits 19 and 22 can be read by software ('1'
when on, '0' when off). The table below lists the number of PCI PIO window
selections available with various RFM‐5565 memory options.
Switch S1
Switch S1
Position 4
Position 3
Size
Off
Off
Off
On
On
Off
On
On
Two registers in PCIBAR0 are used to implement the PCI PIO Sliding Windows.
The LAS1BA register (Direct Slave Local Address Space 1 Range, PCIBAR0 Offset
$F0) is read‐only. It is determined by switch settings and the installed memory
option. The LAS1RR (Remap) register (Direct Slave Local Address Space 1 Local
Base Address, PCIBAR0 Offset $F4) is writeable in bits 27:21. The 32‐bit register
masks off invalid upper and lower bits based on switch and installed memory
settings (defaults to $00000001).
Consider this example with a PCI PIO window set to 2 MByte. First, the firmware
will set the range register to $FFE00000 to indicate a 2 MByte PCI PIO window.
Next, the system (BIOS) will set the PCI Base Address (PCIBAR3) on a 2 MByte
boundary. For example, the BIOS could set the PCIBAR3 to $F7600000 (allowing a
PCI window up to $F77FFFFF). This serves as the PCI Base Address for PIO
access to the local Reflective Memory address space. The firmware also defaults
setting the Remap Value to 0 at the beginning of the installed memory address
Number of
LCSR1
LCSR1
PIO Windows
bit-22
bit-19
with 64 MByte
0
0
1
0
1
1
1
0
4
1
1
32
Number of
Number of
PCI Windows
PIO Windows
with 128 MByte
with 256 MByte
1
1
2
4
8
16
64
128
Programming 64
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