Board Revision Register; Board Id Register; Board Revision Build Register; Node Id Register - GE PCIE-5565PIORC* Hardware Reference Manual

Ultrahigh speed fiber-optic reflective memory with interrupts
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Table 3-52 Local Control and Status Register 1

Bit 31
Status LED
Bit 23
Reserved
Bit 15
Bit 07
TX FIFO Empty TX FIFO Almost
50 PCIE-5565PIORC Reflective Memory Board

3.3.1 Board Revision Register

Board Revision (BRV) BAR2 (Offset $0): An 8‐bit register used to represent 
revisions or model numbers. This register is read‐only.

3.3.2 Board ID Register

Board ID (BID) BAR2 (Offset $1): An 8‐bit register which contains an 8‐bit code 
unique to the RFM‐5565 type boards. The code is $65. This register is read‐only.

3.3.3 Board Revision Build Register

Board Revision Build (BRB) BAR2 (Offset $2): A 16‐bit register used to represent 
the build number for this specific revision. The upper four bits indicate the PCI 
memory window size corresponding to the FPGA configuration file currently 
loaded. This register is read‐only.
– 1 = 2 MB memory window
– 2 = 16 MB memory window
– 3 = 64 MB memory window
– 4 = 128 MB memory window
– 5 = 256 MB memory window

3.3.4 Node ID Register

Node ID (NID) BAR2 (Offset $4): An 8‐bit register containing the node ID of the 
board. This register reflects the setting of the onboard switch S2 and is read‐only. 
Each board on a network must have a unique node ID.

3.3.5 Local Control and Status Register 1

Local Control and Status Register 1 (LCSR1) BAR2 (Offset $08): A 32‐bit register 
containing Reflective Memory control and status bits is described below.
Bit 30
Bit 29
Transmitter
Dark-on-Dark
Disable
Enable
Bit 22
Bit 21
S1-4 PCI
Config 1
Window
Switch 4
Bit 14
Bit 13
Bit 06
Bit 05
Latched RX
Full
FIFO Full
LCSR1: BAR2 Offset $08
Bit 28
Bit 27
Bit 26
Loopback
Local
Redundant
Enable
Memory
Mode Enabled
Parity
Enable
Bit 20
Bit 19
Bit 18
Config 0
S1-3 PCI
S1-2 Delay TX
Window
from PCI write
Switch 3
Bit 12
Bit 11
Bit 10
Reserved
Bit 04
Bit 03
Bit 02
Latched RX
Latched
RX Signal
FIFO Almost
Sync Loss
Detect
Full
Bit 25
Bit 24
Rogue Master
Rogue Master 0
1 Enabled
Enabled
Bit 17
Bit 16
Offset 1
Offset 0
Bit 09
Bit 08
Bit 01
Bit 00
Bad Data
Own Data

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