Network Target Data Register; Network Target Node Register; Table 3-54 Local Interrupt Enable Register - GE PCIE-5565PIORC* Hardware Reference Manual

Local Interrupt Enable Register
Local Interrupt Enable Register (LIER) BAR2 (Offset $14): A 32‐bit register
containing a group of interrupt enables corresponding to the status bits in LISR.

Table 3-54 Local Interrupt Enable Register

Bit 31 Bit 30 Bit 29
Bit 23 Bit 22 Bit 21
Bit 15 Bit 14 Bit 13
Auto Clear Reserved Enable Int on
Enable Local Memory
Parity Error
Bit 07 Bit 06 Bit 05
Enable Int Enable Int on Enable Int on
on Pending Rogue Packet TX FIFO Full
Net. Int. 4 Fault

3.3.7 Network Target Data Register

Network Target Data (NTD) BAR2 (Offset $18): A 32‐bit register containing the
data associated with one of the four network interrupts that will be sent to the
target (destination) node. Writing data to this register does not initiate the actual
interrupt; only writing to the Network Interrupt Command (NIC) register will do
so. The NTD register is both read and write accessible.

3.3.8 Network Target Node Register

Network Target Node (NTN) BAR2 (Offset $1C): An 8‐bit register containing the
node ID of the target (destination) node. Writing to the NTN register does not
initiate the actual network interrupt. This register is both read and write
accessible. The NTN register can be written or read with the Network Interrupt
Command Register as a single 16‐bit word.
LIER: BAR2 Offset $14
Bit 28 Bit 27 Bit 26
Reserved
Bit 20 Bit 19 Bit 18
Reserved
Bit 12 Bit 11 Bit 10
Enable Int Enable Int Enable Int
on Memory on Latched on RX FIFO
Write Inhibit Sync Loss Full
Bit 04 Bit 03 Bit 02
Reserved Enable Int Enable Int
on Reset on Pending
Node Net. Int. 3
Request
Bit 25 Bit 24
Bit 17 Bit 16
Bit 09 Bit 08
Enable Int Enable Int
on RX FIFO on Bad
Almost Full Data
Bit 01 Bit 00
Enable Int Enable Int
on Pending on Pending
Net. Int. 2 Net. Int. 1
Programming 57